module Demo1(
        CLOCK_50,						//	On Board 50 MHz
		// Your inputs and outputs here
        SW,
        KEY,
		// The ports below are for the VGA output.  Do not change.
		VGA_CLK,   						//	VGA Clock
		VGA_HS,							//	VGA H_SYNC
		VGA_VS,							//	VGA V_SYNC
		VGA_BLANK_N,						//	VGA BLANK
		VGA_SYNC_N,						//	VGA SYNC
		VGA_R,   						//	VGA Red[9:0]
		VGA_G,	 						//	VGA Green[9:0]
		VGA_B   						//	VGA Blue[9:0]
                    );

	input			CLOCK_50;				//	50 MHz
	input   [9:0]   SW;
	input   [3:0]   KEY;

	// Declare your inputs and outputs here
	// Do not change the following outputs
	output			VGA_CLK;   				//	VGA Clock
	output			VGA_HS;					//	VGA H_SYNC
	output			VGA_VS;					//	VGA V_SYNC
	output			VGA_BLANK_N;				//	VGA BLANK
	output			VGA_SYNC_N;				//	VGA SYNC
	output	[9:0]	VGA_R;   				//	VGA Red[9:0]
	output	[9:0]	VGA_G;	 				//	VGA Green[9:0]
	output	[9:0]	VGA_B;   				//	VGA Blue[9:0]

    wire clk;
    assign clk = CLOCK_50;
	wire [2:0] colour;
	wire [7:0] x;
	wire [6:0] y;
	wire write_en;
	wire reset_n;
	assign reset_n = KEY[3];


    // Create an Instance of a VGA controller - there can be only one!
	// Define the number of colours as well as the initial background
	// image file (.MIF) for the controller.
	/*
    vga_adapter VGA(
			.resetn(reset_n),
			.clock(CLOCK_50),
			.colour(colour),
			.x(x),
			.y(y),
			.plot(write_en),
			// Signals for the DAC to drive the monitor.
			.VGA_R(VGA_R),
			.VGA_G(VGA_G),
			.VGA_B(VGA_B),
			.VGA_HS(VGA_HS),
			.VGA_VS(VGA_VS),
			.VGA_BLANK(VGA_BLANK_N),
			.VGA_SYNC(VGA_SYNC_N),
			.VGA_CLK(VGA_CLK)
            );

		defparam VGA.RESOLUTION = "160x120";
		defparam VGA.MONOCHROME = "FALSE";
		defparam VGA.BITS_PER_COLOUR_CHANNEL = 1;
		defparam VGA.BACKGROUND_IMAGE = "black.mif";
      */

    wire draw, clear, save, go, dd_done, dump, wait_prime, waiting;
    wire [7:0] count, offset;
    wire [3:0] state;
    wire [2:0] amp, past_amp, curr_amp, futr_amp;
    wire [1:0] segment, mode;


    draw_control dc1(
        .clk(clk),
        .reset_n(reset_n),
        .clear_done(dd_done),   //dd_done
        .draw_done(dd_done),
        .go(go),           //from enable generator
        .clear(clear),
        .waiting(waiting),
        .draw(draw),
        .save(save),
        .segment(segment),
        .current_state(state),
        .wait_prime(wait_prime),
        .offset(offset),
        .write_en(write_en)
    );

    wave_control wc1(   //temp needs to be read from music
        .clk(clk),
        .reset_n(reset_n),
        .amp_in(SW[1:0]),
        .amp_out(amp)
    );

    draw_driver dd1(
        .clk(clk),
        .reset_n(reset_n),
        .go(go),
        .waiting(waiting),
        .flag(dd_done),
        .q(count),
        .out_clk(dd_done)
        );

    wave_datapath wd1(
        .clk(clk),
        .reset_n(reset_n),
        .beat_sig(KEY[0]),
        .amp(amp),
        .past_amp(past_amp),
        .curr_amp(curr_amp),
        .futr_amp(futr_amp)
    );

    interpret i1(
        .clk(clk),
        .reset_n(reset_n),
        .past_amp(past_amp),
        .curr_amp(curr_amp),
        .futr_amp(futr_amp),
        .count(count),
        .segment(segment),
        .draw(draw),
        .clear(clear),
        .offset(offset),
        .x(x),
        .y(y)
    );

    enable_generator eg1(
        .clk(clk),
        .reset_n(reset_n),
        .state(state),
        .clear(clear),
        .draw(draw),
        .pamp(past_amp),
        .camp(curr_amp),
        .famp(futr_amp),
        .wait_prime(wait_prime),
        .go(go)
    );

    colour_controller cc1(
        .clk(clk),
        .reset_n(reset_n),
        .in_mode(SW[9:8]),
        .out_mode(mode)
    );

    colour_datapath cd1(
        .clk(clk),
        .reset_n(reset_n),
        .mode(mode),
        .amp(amp),
        .wait_prime(wait_prime),
        .count(count),
        .draw(draw),
        .clear(clear),
        .colour(colour)
    );


endmodule

// dc1
module draw_control(
	input clk,
	input reset_n,
	input clear_done,
	input draw_done,
	input go,
	output reg clear,
	output reg draw,
    output reg waiting,
	output reg save,
	output reg [1:0] segment,
	output reg [3:0] current_state,
    output reg wait_prime,
    output reg [7:0] offset,
    output reg write_en
    );

    reg [3:0] next_state;

	localparam  S_WAIT11   	=   4'd0;   //wait (default case)
	localparam  S_CLEAR1    = 	4'd1;	//clear segment 1
	localparam  S_WAIT12   	=   4'd2;   //wait inbetween 1
	localparam  S_DRAW1		=	4'd3;	//draw segment 1
    localparam  S_WAIT21    =   4'd4;   //wait to redraw segment 2
	localparam  S_CLEAR2	= 	4'd5;	//clear segment 2
	localparam  S_WAIT22   	=   4'd6;   //wait inbetween 2
	localparam  S_DRAW2		=	4'd7;	//draw segment 2
    localparam  S_WAIT31    =   4'd8;   //wait to redraw segment 3
	localparam  S_CLEAR3	= 	4'd9;	//clear segment 3
	localparam  S_WAIT32   	=   4'd10;  //wait inbetween 3
	localparam  S_DRAW3		=	4'd11;	//draw segment 3

    // Next state logic aka our state table
   always@(posedge clk, posedge go)
	begin: state_table
			case(current_state)
				S_WAIT11: next_state = go           ? S_CLEAR1  : S_WAIT11;
				S_CLEAR1: next_state = clear_done   ? S_WAIT12  : S_CLEAR1;
				S_WAIT12: next_state = go           ? S_DRAW1   : S_WAIT12;
				S_DRAW1 : next_state = draw_done    ? S_WAIT21  : S_DRAW1;
				S_WAIT21: next_state = go           ? S_CLEAR2  : S_WAIT21;
				S_CLEAR2: next_state = clear_done   ? S_WAIT22  : S_CLEAR2;
				S_WAIT22: next_state = go           ? S_DRAW2   : S_WAIT22;
				S_DRAW2 : next_state = draw_done    ? S_WAIT31  : S_DRAW2;
				S_WAIT31: next_state = go           ? S_CLEAR3  : S_WAIT31;
				S_CLEAR3: next_state = clear_done   ? S_WAIT32  : S_CLEAR3;
				S_WAIT32: next_state = go           ? S_DRAW3   : S_WAIT32;
				S_DRAW3 : next_state = draw_done    ? S_WAIT11  : S_DRAW3;
		endcase
    end // state_table

    // Output logic aka all of our datapath control signals
    always @(*)
    begin: enable_signals
        case (current_state)
            S_WAIT11: begin
                offset <= 8'b0;
                wait_prime <= 1;
                waiting <= 1;
                clear <= 0;
                draw <= 0;
                save <= 0;
                segment <= 2'b10;
                write_en <= 1'b0;
            end
            S_CLEAR1: begin
                offset <= 8'b0;
                wait_prime <= 0;
                waiting <= 0;
                clear <= 1;
                draw <= 0;
                save <= 0;
                segment <= 2'b00;
                write_en <= 1'b1;
            end
            S_WAIT12: begin
                offset <= 8'b0;
                wait_prime <= 0;
                waiting <= 1;
                clear <= 0;
                draw <= 0;
                save <= 0;
                segment <= 2'b10;
                write_en <= 1'b0;
            end
            S_DRAW1: begin
                offset <= 8'b0;
                wait_prime <= 0;
                waiting <= 0;
                clear <= 0;
                draw <= 1;
                save <= 1;
                segment <= 2'b00;
                write_en <= 1'b1;
            end
            S_WAIT21: begin
                offset <= 8'd53;
                wait_prime <= 0;
                waiting <= 1;
                clear <= 0;
                draw <= 0;
                save <= 0;
                segment <= 2'b01;
                write_en <= 1'b0;
            end
            S_CLEAR2: begin
                offset <= 8'd53;
                wait_prime <= 0;
                waiting <= 0;
                clear <= 1;
                draw <= 0;
                save <= 0;
                segment <= 2'b01;
                write_en <= 1'b1;
            end
            S_WAIT22: begin
                offset <= 8'd53;
                wait_prime <= 0;
                waiting <= 1;
                clear <= 0;
                draw <= 0;
                save <= 0;
                segment <= 2'b01;
                write_en <= 1'b0;
            end
            S_DRAW2: begin
                offset <= 8'd53;
                wait_prime <= 0;
                waiting <= 0;
                clear <= 0;
                draw <= 1;
                save <= 1;
                segment <= 2'b01;
                write_en <= 1'b1;
            end
            S_WAIT31: begin
                offset <= 8'd106;
                wait_prime <= 0;
                waiting <= 1;
                clear <= 0;
                draw <= 0;
                save <= 0;
                segment <= 2'b10;
                write_en <= 1'b0;
            end
            S_CLEAR3: begin
                offset <= 8'd106;
                wait_prime <= 0;
                waiting <= 0;
                clear <= 1;
                draw <= 0;
                save <= 0;
                segment <= 2'b10;
                write_en <= 1'b1;
            end
            S_WAIT31: begin
                offset <= 8'd106;
                wait_prime <= 0;
                waiting <= 1;
                clear <= 0;
                draw <= 0;
                save <= 0;
                segment <= 2'b10;
                write_en <= 1'b0;
            end
            S_DRAW3: begin
                offset <= 8'd106;
                wait_prime <= 0;
                waiting <= 0;
                clear <= 0;
                draw <= 1;
                save <= 1;
                segment <= 2'b10;
                write_en <= 1'b1;
            end
			default begin
                wait_prime <= 0;
                waiting <= 1;
                clear <= 0;
				draw<= 0;
                save <= 0;
                segment <= 2'b11;
                write_en <= 1'b0;
			end
        endcase
    end // enable_signals

    // current_state registers
    always@(posedge clk)
    begin: state_FFs
        if(!reset_n)
            current_state <= S_WAIT11;
        else
            current_state <= next_state;
    end // state_FFS
endmodule

// wc1
module wave_control(
    input clk,
    input reset_n,
    //input enable,
    input [1:0] amp_in,
    output reg [2:0] amp_out
    //output reg play
    );

    reg [2:0] current_state, next_state;

    // Next state logic aka our state table
    always@(posedge clk)begin//: state_table
        //if(enable)
            next_state <= {1'b0,amp_in};
            amp_out <= current_state;
        //else
        //    next_state <= current_state;
    end // state_table

    // current_state registers
    always@(posedge clk)
    begin: state_FFs
        if(!reset_n)
            current_state <= 2'b00;
        else
            current_state <= next_state;
    end // state_FFS
endmodule

// dd1
module draw_driver(
    input clk,
    input reset_n,
    input go,
    input waiting,
    input flag,
    output reg[7:0] q,
    output reg out_clk
    );
    reg running;

    always@(posedge go, posedge flag)begin
        if(flag == 1'b1)
            running <= 0;
        else if(go == 1'b1)
            running <= 1;
        else
            running <= 0;
    end

    always @(posedge clk, negedge reset_n)begin
		if(reset_n == 1'b0)begin
		    q<=8'd55;
			out_clk <= 0;
		end
	    else if(running == 1'b1 && !waiting) begin
            q<=q-8'b1;
            if(q == 8'd0)begin
                out_clk <= 1;
            end
        end
        else begin
            q<=8'd55;
            out_clk <= 0;
        end
    end
endmodule

// wd1
module wave_datapath(
    input clk,
    input reset_n,
    input beat_sig,
    input [2:0] amp,
    output reg [2:0] past_amp,
    output reg [2:0] curr_amp,
    output reg [2:0] futr_amp
    );

    reg [2:0] next_curr, next_past;

    always@(negedge reset_n, posedge beat_sig) begin
        if(!reset_n)begin
            next_past <= 3'b0;
            next_curr <= 3'b0;
        end
        else begin
            next_past <= next_curr;
            next_curr <= amp;
        end
    end

    // Set the amplifiers
    always @ (posedge clk, posedge beat_sig) begin
        if(!reset_n)begin
            past_amp <= 3'b0;
            curr_amp <= 3'b0;
            futr_amp <= 3'b0;
        end
        past_amp <= next_past;
        curr_amp <= next_curr;
        futr_amp <= amp;
    end
endmodule

//need to implement this

// i1
module interpret(
    input clk,
    input reset_n,
    input[2:0] past_amp,
    input[2:0] curr_amp,
    input[2:0] futr_amp,
    input[7:0] count,
    input [1:0] segment,
	input draw,
    input clear,
    input [7:0] offset,
    output reg [7:0] x,
    output reg [6:0] y
    );

    reg [2:0] left_seg;
    reg [2:0] midl_seg;
    reg [2:0] righ_seg;

    localparam y_pos = 7'd110;
    localparam y_dif = 7'd20;

    always@ (posedge clk or negedge reset_n)begin
        if(reset_n == 1'b0)begin
            left_seg <= 3'b0;
            midl_seg <= 3'b0;
            righ_seg <= 3'b0;
            x <= 8'b0;
            y <= 7'b0;
        end
		else if(draw == 1'b1) begin
            x <= count+offset;
            case(segment)
                2'b00:begin
                    left_seg <= past_amp;
                    y <= y_pos-(y_dif*past_amp);
                end
                2'b01:begin
                    midl_seg <= curr_amp;
                    y <= y_pos-(y_dif*curr_amp);
                end
                2'b10:begin
                    righ_seg <= futr_amp;
                    y <= y_pos-(y_dif*futr_amp);
                end
                default: begin
                end
            endcase

		end
        else if(clear == 1'b1)begin
            x<=count+offset;
            case(segment)
                2'b00: y <= y_pos-(y_dif*left_seg);
                2'b01: y <= y_pos-(y_dif*midl_seg);
                2'b10: y <= y_pos-(y_dif*righ_seg);
                default y<= y_pos;
            endcase
        end
		else begin
			x <= 8'b0;
			y <= 7'b0;
		end
	 end
endmodule


// eg1
module enable_generator(
    input clk,
    input reset_n,
    input clear,
    input draw,
    input [3:0] state,
    input [2:0] pamp,
    input [2:0] camp,
    input [2:0] famp,
    input wait_prime,
    output reg go
    );

    reg [2:0] prev_pamp;
    reg [2:0] prev_camp;
    reg [2:0] prev_famp;
    reg [3:0] prev_state;

    always@(posedge clk)begin
        if(reset_n == 1'b0)begin
            go <= 1'b0;
            prev_state <= state;
            prev_pamp <= pamp;
            prev_camp <= camp;
            prev_famp <= famp;
        end
        else if (state != prev_state && !wait_prime && !clear && !draw)begin
            go <= !go;
        end
        else if (pamp != prev_pamp)begin
            go <= !go;
        end
        else if (camp != prev_camp)begin
            go <= !go;
        end
        else if (famp != prev_famp)begin
            go <= !go;
        end
        else
            go = 1'b0;
            prev_state <= state;
            prev_pamp <= pamp;
            prev_camp <= camp;
            prev_famp <= famp;
        end
endmodule

//cc1
module colour_controller(
    input clk,
    input reset_n,
    input [1:0] in_mode,
    output reg [1:0] out_mode
    );

    reg [1:0] current_state, next_state;

    // Next state logic aka our state table
    always@(posedge clk)begin//: state_table
        next_state <= in_mode;
        out_mode <= current_state;
    end // state_table

    // current_state registers
    always@(posedge clk)
    begin: state_FFs
        if(!reset_n)
            current_state <= 2'b00;
        else
            current_state <= next_state;
    end // state_FFS
endmodule

//cd1
module colour_datapath(
    input clk,
    input reset_n,
    input [1:0] mode,
    input [2:0] amp,
    input wait_prime,
    input [7:0] count,
    input draw,
    input clear,
    output reg [2:0] colour
    );

    reg [3:0] wait_colour;
    always@(negedge wait_prime) begin
        if(!reset_n)
            wait_colour <= 3'b000;
        else
            wait_colour <= wait_colour + 3'b1;
    end


    always@(posedge clk)begin
        if(!reset_n)
            colour <= 3'b000;
        else begin
            if(clear == 1'b1)
                colour <= 3'b000;
            else if(draw == 1'b1)begin
                case(mode)
                    2'b00: colour <= 3'b111;
                    2'b01:begin
                        case(amp)
                            3'b000: colour <= 3'b001;
                            3'b001: colour <= 3'b011;
                            3'b010: colour <= 3'b010;
                            3'b011: colour <= 3'b111;
                            default: colour <= 3'b000;
                        endcase
                    end
                    2'b10: colour <= ((count % 6) + wait_colour);
                    2'b11: colour <= wait_colour;
                    default:colour <= 3'b000;
                endcase
            end
            else
                colour <= 3'b000;
        end
    end
endmodule