library ieee;
   use ieee.std_logic_1164.all;
   use ieee.std_logic_unsigned.all;
   use ieee.numeric_std.all;

   type MyRecordType is record
     x : std_logic_vector(2 downto 0);
     y : std_logic_vector(2 downto 0);
   end record;

   entity Test is
     port(
       clk : in std_logic;
       input : in MyRecordType;
           output : out std_logic
     );
   end entity;

   architecture RTL of Test is

   begin
     process (clk) is
     begin
       if rising_edge(clk) then
             if (input.x = input.y) then
                   output <= '1';
                 else
                   output <= '0';
                 end if;
           end if;
     end process;
   end;

library ieee;
   use ieee.std_logic_1164.all;
   use ieee.std_logic_unsigned.all;
   use ieee.numeric_std.all;

   entity TOP is
   end entity;

   architecture SIM of TOP is

          type MyRecordType is record
                 x : std_logic_vector(2 downto 0);
                 y : std_logic_vector(2 downto 0);
          end record;

          component Test is
                 port(
                        clk    : in  std_logic;
                        input  : in  MyRecordType;
                        output : out std_logic
                 );
          end component;

          constant period : time := 20 ns;
          signal clk      : std_logic;
          signal result   : std_logic;
          signal myRecord : MyRecordType;

   begin
          dut : Test port map(clk => clk, input => myRecord, output => result);

          clk <= not clk after period / 2;

          process is
          begin
                 myRecord.x <= "000";
                 myRecord.y <= "000";

                 wait for 20 ns;

                 if result = 0 then
                        report "TEST 1 - FAILED.";
                 else
                        report "TEST 1 - PASSED.";
                 end if;

                 myRecord.x <= "000";
                 myRecord.y <= "010";

                 wait for 20 ns;

                 if result = 1 then
                        report "TEST 2 - FAILED.";
                 else
                        report "TEST 2 - PASSED.";
                 end if;

                 wait;

          end process;

   end architecture;