module top(

    //////////// CLOCK //////////
    input  CLOCK_50,
    input  CLOCK_LOC,
    output CLOCK_SYNC,
    //input CLOCK_SYNC,

    //////////// SDRAM1 //////////
    output [1:0] SDRAM1_BA,
    output [12:0] SDRAM1_A,
    output SDRAM1_CKE,
    output SDRAM1_CLK,
    output SDRAM1_CS,
    output SDRAM1_CAS,
    output SDRAM1_RAS,
    output SDRAM1_WE,
    output [1:0]  SDRAM1_DQM,
    inout  [15:0] SDRAM1_D,

    //////////// SDRAM2 //////////
    output [14:0] SDRAM2_A,
    output SDRAM2_CKE,
    output SDRAM2_CLK,
    output SDRAM2_CS,
    output SDRAM2_CAS,
    output SDRAM2_RAS,
    output SDRAM2_WE,
    output [1:0]  SDRAM2_DQM,
    inout  [15:0] SDRAM2_D,

    //////////// QBUS //////////
    output          QB_DEN,
    output reg [17:0]   QB_DIN,
    output reg  QB_TCLK,

    output          QB_REN,
    input  [17:0]   QB_ROUT,
    input           QB_RCLK,

    //////////// CH1_IM //////////
    input  [17:0] CH1_IM,
    //////////// CH1_RE //////////
    input  [17:0] CH1_RE,

    //////////// CH2_IM //////////
    //input  [17:0] CH2_IM,
    //////////// CH2_RE //////////
    //input  [17:0] CH2_RE,

    input        CH1_RCLK,
    output       CH1_REN,
    input        CH2_RCLK,
    output       CH2_REN,
    /*input          CH3_RCLK,
    output       CH3_REN,
    input        CH4_RCLK,
    output       CH4_REN,
    input        CH5_RCLK,
    output       CH5_REN,
    input        CH6_RCLK,
    output       CH6_REN,
    input        CH7_RCLK,
    output       CH7_REN,
    input        CH8_RCLK,
    output       CH8_REN,*/

    //////////// USB_FT //////////
    input [7:0] USB_FT_ACBUS,

    input USB_FT_nRXF,
    input USB_FT_nTXE,
    input USB_FT_nRD,
    output reg USB_FT_nWR,
    input USB_FT_CLKIN,
    output reg USB_FT_nOE = 1,
    output [7:0] USB_FT_D,

    //////////// USB_FT //////////
    //output         UC_CLK,
    //output         UC_ALE,
    //output [7:0] UC_P0,
    //output [7:0] UC_P1,
    //output [7:0] UC_P2,
    //output [7:0] UC_P3,

    //////////// MAXV //////////
    //output    MAXV_SPI_SCK,
    //input     MAXV_SPI_MISO,
    //output    MAXV_SPI_MOSI,
    //output    MAXV_SPI_SS,

    //output    MAXV_CLOCK,
    //input     MAXV_IRQ,


    //////////// MAXV //////////
    //output    I2C_CLK,
    //inout     I2C_SDA,

    //////////// CARU //////////
    //output    CARU_EN,

    //input     CARU_C_IN,
    //input     CARU_D_IN,
    //output    CARU_C_OUT,
    //output    CARU_D_OUT,

    //////////// SPI //////////
    //input     SPI_SCLK,
    //output    SPI_MISO,
    //input     SPI_MOSI,
    //input     SPI_CS,

    //input     DS,
    //input     TI,

    //////////// SIGNALS //////////
    //output X6_ENA,
    //output X6_TAU_OBM,
    //output X6_ISCHP,
    //output X6_ISCHP_OP,
    //output X6_KO,

    //////////// SIGNALS //////////
    /*output X29_ENA,
    input X24_IBP,
    input X24_SYNTH_OK,
    input X24_MFS_OK,*/

    //////////// CONN20 //////////
    input CONN20_TIM1,
    input CONN20_TIM2,
    input CONN20_TIM3,
    input CONN20_IZP,


    //////////// SIGNALS //////////
    //output PRD_OK,
    //output VIP_OK,
    //output TR_OK,
    //output NADD1_OK,
    //output MOD_OK,
    //output P3_OK,
    //output P1_OK,
    //output POUT_OK,

    //////////// SIGNALS //////////
    /*output X27_ENA,
    input X27_ADC1_OL,
    input X27_ADC2_OL,
    input X27_ADC3_OL,
    input X27_ADC4_OL,

    input X27_ADC1_OK,
    input X27_ADC2_OK,
    input X27_ADC3_OK,
    input X27_ADC4_OK,

    input X27_SHU_OK,
    input X27_PS_OK,
    input X27_SOCHI_OK,
    input X27_CARU_OK,
    input X27_IP32_OK,

    input X27_DET41,
    input X27_DET42,
    input X27_DET43,
    input X27_DET44,

    input X27_DET31,
    input X27_DET32,
    input X27_DET33,
    input X27_DET34,

    input X27_DET21,
    input X27_DET22,
    input X27_DET23,
    input X27_DET24,

    input X27_DET11,
    input X27_DET12,
    input X27_DET13,
    input X27_DET14,*/

    //////////// SIGNALS //////////
    //output X8_X11_ENA,
    //output X8_IV,
    //output X11_D0,

    //
    output reg GPIO0,
    output reg GPIO1


);

reg [31:0] count = 0;

reg [1:0] ind = 0;

//assign GPIO0 = CLOCK_LOC; //USB_FT_CLKIN;

assign CLOCK_SYNC = 1;

assign QB_DEN = 1;
assign QB_REN = 1;

assign CH2_REN = 1;

reg clkDelim;


reg fifoUsbTxWrReq;
//reg fifoUsbTxRdReq;
wire fifoUsbTxRdEmpty;
//wire fifoUsbTxRdReq = (USB_FT_nTXE==0)&&(fifoUsbTxRdEmpty==0);
wire fifoUsbTxRdReq = (USB_FT_nTXE==0);
wire fifoUsbTxWrFull;

//fifo_lv_rx fifoUsbTx(.data(dataIn), .wrclk(CLOCK_LOC), .wrreq(clkCnt[1]),
//                      .q(USB_FT_D), .rdclk(USB_FT_CLKIN), .rdreq(fifoUsbTxRdReq), .rdempty(fifoUsbTxRdEmpty));

fifo_lv_rx fifoUsbTx(.data(fifoWrCnt), .wrclk(CLOCK_LOC), .wrreq(fifoUsbTxWrReq), .wrfull(fifoUsbTxWrFull),
                        .q(USB_FT_D), .rdclk(USB_FT_CLKIN), .rdreq(fifoUsbTxRdReq), .rdempty(fifoUsbTxRdEmpty));


//fifo_lv_rx fifoUsbTx(.data(QB_ROUT[15:0]), .wrclk(QB_RCLK), .wrreq(QB_RCLK),
//                      .q(USB_FT_D), .rdclk(USB_FT_CLKIN), .rdreq(fifoUsbTxRdReq), .rdempty(fifoUsbTxRdEmpty));

//assign USB_FT_nWR = !((USB_FT_nTXE==0) &&(fifoUsbTxRdEmpty==0));
always @(posedge USB_FT_CLKIN) begin
    USB_FT_nWR <= !((USB_FT_nTXE==0) &&(fifoUsbTxRdEmpty==0));
end


always @(posedge USB_FT_CLKIN) begin

    //
    //USB_FT_nWR <= USB_FT_nTXE;


    if((USB_FT_nWR  == 0) && (USB_FT_nTXE == 0)) begin

        //USB_FT_D <= count>>(8*ind);
        //USB_FT_D <= rClkCount;
        //USB_FT_D <= dataIn;
        //USB_FT_D <= count[7:0];
        //USB_FT_D <= CH1_IM[7:0];
        //USB_FT_D <= ch1ClkCnt[7:0];
        //USB_FT_D <= CH1_RE[7:0];
        //USB_FT_D <= CH1_RE>>(8*ind);

        //USB_FT_D <= dataIn>>(8*count[0]);



        count <= count + 1;
        if(ind == 3) begin
            ind <= 0;
            //count <= count + 1;
            //USB_FT_D <= ch2ClkCnt[7:0];
        end
        else begin
            ind <= ind + 1;
            //USB_FT_D <= ch1ClkCnt[7:0];
        end

        if(count[0] == 0) begin
            //USB_FT_D <= dataIn[7:0];
        end
        else begin
            //USB_FT_D <= dataIn[15:8];
        end

    end


    //clkDelim <= !clkDelim ;
    // <= clkDelim;


end

reg [31:0] clockCounter;
reg lastState = 0;
reg [4:0] clkCnt;

reg [15:0] fifoWrCnt = 0;
//assign GPIO0 = CLOCK_LOC;
//assign QB_TCLK  = CLOCK_LOC;
always @(posedge CLOCK_LOC) begin
    GPIO0 <= !GPIO0;
    QB_TCLK <= !QB_TCLK;
    //QB_TCLK <= clkCnt[4];
    clkCnt <= clkCnt + 1;

    clockCounter <= clockCounter + 1;

    //if((clockCounter[3] == 1) & (clockCounter[0] == 1)) begin
    lastState <= clockCounter[3];
    if((clockCounter[3] == 1) && (lastState == 0)) begin
        GPIO1 <= 1;
        fifoWrCnt <= fifoWrCnt + 1;
        fifoUsbTxWrReq <= 1;
    //  QB_TCLK <= 1;
    end
    else begin
        fifoUsbTxWrReq <= 0;
        GPIO1 <= 0;
//      QB_TCLK <= 0;
    end
end

reg dataRecv = 0;
reg [15:0] dataOut = 0;

reg [17:0] dataOutArr [5:0];
always @(posedge QB_TCLK) begin
    dataOut <= dataOut + 1;
    QB_DIN <= dataOut;
    dataRecv <= 1;
    //QB_DIN <= 18'b000000000111111111;
end


reg [17:0] dataIn;
reg [8:0] rClkCount = 0;
always @(posedge QB_RCLK) begin
    dataIn <= QB_ROUT;
    rClkCount <= rClkCount + 1;
end


always @(posedge CH2_RCLK) begin
    //dataIn <= CH1_RE;

end


reg [31:0] ch1ClkCnt = 0;
always @(posedge CH1_RCLK) begin
    //dataIn <= CH1_RE;
    ch1ClkCnt <= ch1ClkCnt + 1;

end

reg [31:0] ch2ClkCnt = 0;
always @(posedge CH2_RCLK) begin
    //dataIn <= CH1_RE;
    ch2ClkCnt <= ch2ClkCnt + 1;

end




endmodule