library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity NUMARATOR is
Port(rst: in STD_LOGIC;
clk: in STD_LOGIC;
q: out STD_LOGIC_VECTOR(3 DOWNTO 0));
end NUMARATOR;

architecture NUMARATOR of NUMARATOR is
begin
     Process(clk,rst)
     variable count: STD_LOGIC_VECTOR:="0000";
     begin
     if(rst='1') then
     q<="0000";
     elsif(rising_edge(clk)) then
     if(count<"1001") then
     count:=count+"1";
     q<=count;
     else
     q<="0000";
     end if;
   end if;
  end Process;
end NUMARATOR;