module automat_0101
(
input x, clk, reset,
output reg y,
output LED
);
wire slow_clk
reg [26:0] div_clk;

always@(posedge clk,posedge reset)

if(reset)
	div_clk <= 0;
else
	div_clk <= div_clk +1;

assign slow_clk = div_clk[26];
assign LED=slow_clk;

reg[2:0] aut_reg, aut_next;
localparam s0=0,s1=1,s2=2,s3=3,s4=4;

always@(*)
	case(aut_reg)
		s0: if(x) aut_next = s0;
			else aut_next = s1;
		s1: if(x) aut_next = s0;
			else aut_next = s2;
		s2: if(x) aut_next = s0;
			else aut_next = s3;
		s3: if(x) aut_next = s4;
			else aut_next = s1;
		s4: if(x) aut_next = s0;
			else aut_next = s1;
		default: aut_next = s0;
	endcase

always@(posedge slow_clk, posedge reset)

if(reset)
	aut_reg <= s0;
else
	aut_reg <= aut_next;
always@(*)
			if(aut_reg==s4)y=1;
			else y=0;
endmodule