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-- Company:
-- Engineer:
--
-- Create Date: 02/22/2019 08:53:00 AM
-- Design Name:
-- Module Name: Addr_3x3 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_unsigned.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.


package bus_multiplexer_pkg is
        type bus_array is array(natural range <>) of std_logic_vector(15 downto 0);
end package;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_unsigned.all;
use work.bus_multiplexer_pkg.all;

entity Addr_flex is

-- FORCED VALUES
-- input_width_max = 64
-- filter size  = 3 x 3

 Port (output : out bus_array(120 downto 0);
        q: in std_logic_vector(15 downto 0)
         );

end Addr_flex;

architecture Behavioral of Addr_flex is

type tmp_array is array(natural range <>) of std_logic_vector(15 downto 0);
    signal t : tmp_array(11 downto 0);
    signal t2 : tmp_array(11 downto 0);



begin
--(q+n*j)%(j*bh)+m

     Tall : FOR m IN 10 DOWNTO 0 GENERATE
        t2(m) <= q+m*64;
	t(m)(9 downto 0) <= t2(m) (9 downto 0);
	t(m)(15 downto 10) <= (others => '0');
        G1 : FOR n IN 10 DOWNTO 0 GENERATE
            output(n+m*11) <= t(m)+n;
        END GENERATE G1;
     END GENERATE Tall;


end Behavioral;