module disp_7seg(b, HEX);
    input [3:0] b;
    output [7:0] HEX;

    assign HEX[0] = (~b[3]&~b[2]&~b[1]&b[0]) | (~b[3]&b[2]&~b[1]&~b[0]);
    assign HEX[1] = (~b[3]&b[2]&~b[1]&b[0]) | (~b[3]&b[2]&b[1]&~b[0]);
    assign HEX[2] = (~b[3]&~b[2]&b[1]&~b[0]);
    assign HEX[3] = (~b[3]&~b[2]&~b[1]&b[0]) | (~b[3]&b[2]&~b[1]&~b[0]) | (~b[3]&b[2]&b[1]&b[0]);
    assign HEX[4] = ~( (~b[3]&~b[2]&~b[1]&~b[0]) | (~b[3]&~b[2]&b[1]&~b[0]) | (~b[3]&b[2]&b[1]&~b[0]) | (b[3]&~b[2]&~b[1]&~b[0])  );
    assign HEX[5] = (~b[3]&~b[2]&~b[1]&b[0]) | (~b[3]&~b[2]&b[1]&~b[0]) | (~b[3]&~b[2]&b[1]&b[0]);
    assign HEX[6] = (~b[3]&~b[2]&~b[1]&~b[0]) | (~b[3]&~b[2]&~b[1]&b[0]) | (~b[3]&b[2]&b[1]&b[0]);
endmodule

// minutos
module firstCounter(Clk, vaiUm, digDir, digEsq);
    input Clk;
    output reg vaiUm;
    output reg [3:0] digDir, digEsq;

    initial begin
        digDir = 4'b0;
        digEsq = 4'b0;
    end

    always @( posedge Clk ) begin
        if(~digEsq[3] & digEsq[2] & ~digEsq[1] & digEsq[0] & digDir[3] & ~digDir[2] & ~digDir[1] & digDir[0] ) begin
            vaiUm = 1;
            digDir = 4'b0;
            digEsq = 4'b0;
        end else begin
            vaiUm = 0;
            if(digDir[0] & ~digDir[1] & ~digDir[2] & digDir[3]) begin // reseta em 9
                digDir = 4'b0;
                digEsq = digEsq + 1;
            end else begin
                digDir = digDir + 1;
            end
        end
    end
endmodule

// horas
module secondCounter(Clk, vaiUm, digDir, digEsq);
    input Clk;
    output reg vaiUm;
    output reg [3:0] digDir, digEsq;

    initial begin
        digDir = 4'b0;
        digEsq = 4'b0;
    end

    always @( posedge Clk ) begin
        if(~digEsq[3] & ~digEsq[2] & digEsq[1] & ~digEsq[0] & ~digDir[3] & ~digDir[2] & digDir[1] & digDir[0]) begin
            vaiUm = 1;
            digDir = 4'b0;
            digEsq = 4'b0;
        end else begin
            vaiUm = 0;
            if(digDir[0] & ~digDir[1] & ~digDir[2] & digDir[3]) begin
                digDir[3:0] = 4'b0;
                digEsq <= digEsq + 1;
            end else begin
                digDir <= digDir + 1;
            end
        end
    end
endmodule


module teste(Clk, HourLef, HourRig, MinLef, MinRig );
    input Clk;
    output [3:0] MinLef, MinRig, HourLef, HourRig;

    wire [1:0] vaiUm;
    firstCounter fc(Clk , vaiUm[0], MinRig, MinLef);
    secondCounter sc(vaiUm[0], vaiUm[1], HourRig, HourLef);
endmodule

module top(SW, KEY, HEX0, HEX1, HEX2, HEX3);
    input [17:0] SW;
    input [3:0] KEY;
    output [7:0] HEX0, HEX1, HEX2, HEX3;

    wire [7:0] left, right;
    teste(KEY[3], left[7:4], left[3:0], right[7:4], right[3:0]);

    disp_7seg d1(right[3:0], HEX0);
    disp_7seg d2(right[7:4], HEX1);
    disp_7seg d3(left[3:0], HEX2);
    disp_7seg d4(left[7:4], HEX3);
endmodule