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- else:
- # LiteDRAM port ------------------------------------------------------------------------
- port = self.sdram.crossbar.get_port()
- port.data_width = 2**int(log2(port.data_width)) # Round to nearest power of 2
- # Parameters ---------------------------------------------------------------------------
- main_ram_size = 2**(geom_settings.bankbits +
- geom_settings.rowbits +
- geom_settings.colbits)*phy.settings.databits//8
- main_ram_size = min(main_ram_size, 0x20000000) # FIXME: limit to 512MB for now
- # Register the memory region (so it shows up in generated .h file):
- self.add_memory_region("main_ram", self.mem_map["main_ram"], main_ram_size)
- # LiteDRAM AXI port --------------------------------------------------------------------
- # FIXME: figure out how to specify offset here!!!
- axi2native = LiteDRAMAXI2Native(self.cpu.mem_axi, port)
- self.submodules += axi2native
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