// Generated by stratus_hls 18.14-s100  (89552.152312)
// Wed Apr  3 12:56:44 2019
// from test.cpp

`timescale 1ps / 1ps


module test(clk, rst, inputs_busy, inputs_vld, inputs_data_in1, outputs_busy, outputs_vld, outputs_data_out1);

      input clk;
      input rst;
      input inputs_vld;
      input [15:0] inputs_data_in1;
      input outputs_busy;
      output inputs_busy;
      output outputs_vld;
      output [15:0] outputs_data_out1;
      reg outputs_m_req_m_prev_trig_req;
      reg outputs_m_unacked_req;
      wire test_Xor_1U_8_4_1_out1;
      wire test_Or_1U_7_4_2_out1;
      reg test_N_Muxb_1_2_9_4_4_out1;
      wire test_And_1U_5_4_11_out1;
      wire test_Not_1U_1_4_10_out1;
      reg inputs_m_unvalidated_req;
      wire test_Or_1U_7_4_8_out1;
      wire test_And_1U_5_4_9_out1;
      reg[1:0] global_state_next;
      wire test_And_1U_5_4_7_out1;
      wire test_Not_1U_1_4_12_out1;
      wire test_Not_1U_1_4_3_out1;
      reg outputs_m_req_m_trig_req;
      reg[1:0] global_state;
      reg stall0;
      reg inputs_m_busy_req_0;

         // resource: mux_1bx2i
         // resource: regr_1
         always @(posedge clk)
          begin :drive_inputs_m_busy_req_0
            if (rst == 1'b0) begin
               inputs_m_busy_req_0 <= 1'd1;
            end
            else begin
               if (stall0) begin
               end
               else begin
                  case (global_state)

                     2'd0, 2'd2:                      begin
                        inputs_m_busy_req_0 <= 1'd0;
                     end

                     2'd1:                      begin
                        inputs_m_busy_req_0 <= 1'd1;
                     end

                  endcase

               end
            end
         end

         // resource: regr_1
         always @(posedge clk)
          begin :drive_outputs_m_req_m_trig_req
            if (rst == 1'b0) begin
               outputs_m_req_m_trig_req <= 1'd0;
            end
            else begin
               if (stall0) begin
               end
               else begin
                  case (global_state)

                     2'd1:                      begin
                        outputs_m_req_m_trig_req <= test_Not_1U_1_4_3_out1;
                     end

                  endcase

               end
            end
         end

         // resource: mux_1bx3i
         always @(test_And_1U_5_4_7_out1 or test_Not_1U_1_4_12_out1 or global_state)
          begin :drive_stall0
            case (global_state)

               2'd1:                begin
                  stall0 = test_Not_1U_1_4_12_out1;
               end

               2'd2:                begin
                  stall0 = test_And_1U_5_4_7_out1;
               end

               default:                begin
                  stall0 = 1'b0;
               end

            endcase

         end

         // resource: regr_2
         always @(posedge clk)
          begin :drive_global_state
            if (rst == 1'b0) begin
               global_state <= 2'd0;
            end
            else begin
               if (stall0) begin
               end
               else begin
                  global_state <= global_state_next;
               end
            end
         end

         // resource: mux_2bx2i
         always @(global_state)
          begin :drive_global_state_next
            case (global_state)

               2'd0, 2'd2:                begin
                  global_state_next = 2'd1;
               end

               default:                begin
                  global_state_next = global_state + 2'd1;
               end

            endcase

         end

         // thread: drive_inputs_busy
         assign inputs_busy = test_And_1U_5_4_9_out1;

         // resource: test_Or_1U_7_4  instance: test_Or_1U_7_4_8
         assign test_Or_1U_7_4_8_out1 = inputs_m_unvalidated_req | inputs_vld;

         // resource: test_And_1U_5_4  instance: test_And_1U_5_4_9
         assign test_And_1U_5_4_9_out1 = test_Or_1U_7_4_8_out1 & inputs_m_busy_req_0;

         // resource: test_Not_1U_1_4  instance: test_Not_1U_1_4_10
         assign test_Not_1U_1_4_10_out1 = !test_And_1U_5_4_9_out1;

         // resource: test_And_1U_5_4  instance: test_And_1U_5_4_11
         assign test_And_1U_5_4_11_out1 = test_Not_1U_1_4_10_out1 & inputs_vld;

         // resource: test_Not_1U_1_4  instance: test_Not_1U_1_4_12
         assign test_Not_1U_1_4_12_out1 = !test_And_1U_5_4_11_out1;

         // resource: regr_1
         always @(posedge clk)
          begin :drive_inputs_m_unvalidated_req
            if (rst == 1'b0) begin
               inputs_m_unvalidated_req <= 1'd1;
            end
            else begin
               inputs_m_unvalidated_req <= test_N_Muxb_1_2_9_4_4_out1;
            end
         end

         // resource:test_N_Muxb_1_2_9_4
         always @(inputs_vld or inputs_m_busy_req_0 or inputs_m_unvalidated_req)
          begin :test_N_Muxb_1_2_9_4_4
            if (inputs_m_busy_req_0) begin
               test_N_Muxb_1_2_9_4_4_out1 = inputs_m_unvalidated_req;
            end
            else begin
               test_N_Muxb_1_2_9_4_4_out1 = inputs_vld;
            end
         end

         // thread: drive_outputs_vld
         assign outputs_vld = test_Or_1U_7_4_2_out1;

         // resource: test_Or_1U_7_4  instance: test_Or_1U_7_4_2
         assign test_Or_1U_7_4_2_out1 = outputs_m_unacked_req | test_Xor_1U_8_4_1_out1;

         // resource: regr_1
         always @(posedge clk)
          begin :drive_outputs_m_unacked_req
            if (rst == 1'b0) begin
               outputs_m_unacked_req <= 1'd0;
            end
            else begin
               outputs_m_unacked_req <= test_And_1U_5_4_7_out1;
            end
         end

         // resource: test_And_1U_5_4  instance: test_And_1U_5_4_7
         assign test_And_1U_5_4_7_out1 = outputs_busy & outputs_vld;

         // resource: test_Xor_1U_8_4  instance: test_Xor_1U_8_4_1
         assign test_Xor_1U_8_4_1_out1 = outputs_m_req_m_trig_req ^ outputs_m_req_m_prev_trig_req;

         // resource: regr_1
         always @(posedge clk)
          begin :drive_outputs_m_req_m_prev_trig_req
            if (rst == 1'b0) begin
               outputs_m_req_m_prev_trig_req <= 1'd0;
            end
            else begin
               outputs_m_req_m_prev_trig_req <= outputs_m_req_m_trig_req;
            end
         end

         // resource: test_Not_1U_1_4  instance: test_Not_1U_1_4_3
         assign test_Not_1U_1_4_3_out1 = !outputs_m_req_m_trig_req;

         // resource: test_Not_1U_1_4  instance: test_Not_1U_1_4_3
         assign outputs_data_out1 = 16'd00000;


endmodule