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  1. Worst Path Information
  2. ***********************
  3.  
  4.  
  5. Path information for path number 1:
  6. Requested Period: 20.000
  7. - Setup time: 0.410
  8. + Clock delay at ending point: 3.360
  9. = Required time: 22.950
  10.  
  11. - Propagation time: 13.785
  12. - Clock delay at starting point: 3.360
  13. = Slack (critical) : 5.805
  14.  
  15. Number of logic level(s): 54
  16. Starting point: or1200_top0.or1200_cpu.or1200_except.ex_freeze_prev / Q
  17. Ending point: or1200_top0.or1200_cpu.or1200_rf.rf_a.mem_mem_0_0 / ADDRARDADDR[5]
  18. The start point is clocked by clk [rising] on pin C
  19. The end point is clocked by clk [rising] on pin CLKARDCLK
  20.  
  21. Instance / Net Pin Pin Arrival No. of
  22. Name Type Name Dir Delay Time Fan Out(s)
  23. -----------------------------------------------------------------------------------------------------------------------------------------------------
  24. or1200_top0.or1200_cpu.or1200_except.ex_freeze_prev FDC Q Out 0.283 3.643 -
  25. ex_freeze_prev Net - - 0.336 - 3
  26. or1200_top0.or1200_cpu.or1200_except.un1_abort_ex_2 LUT5 I4 In - 3.979 -
  27. or1200_top0.or1200_cpu.or1200_except.un1_abort_ex_2 LUT5 O Out 0.330 4.309 -
  28. un1_abort_ex_2 Net - - 0.409 - 7
  29. or1200_top0.or1200_cpu.or1200_except.abort_ex_3 LUT4 I3 In - 4.718 -
  30. or1200_top0.or1200_cpu.or1200_except.abort_ex_3 LUT4 O Out 0.061 4.779 -
  31. abort_ex_0_3 Net - - 0.595 - 86
  32. or1200_top0.or1200_cpu.or1200_sprs.sr_reg_RNIK83D1[0] LUT5 I4 In - 5.374 -
  33. or1200_top0.or1200_cpu.or1200_sprs.sr_reg_RNIK83D1[0] LUT5 O Out 0.061 5.435 -
  34. un2_spr_cs_0_i_0 Net - - 0.475 - 14
  35. or1200_top0.or1200_cpu.or1200_sprs.spr_cs_0_o2[0] LUT6 I5 In - 5.910 -
  36. or1200_top0.or1200_cpu.or1200_sprs.spr_cs_0_o2[0] LUT6 O Out 0.061 5.971 -
  37. N_2016 Net - - 0.490 - 16
  38. or1200_top0.or1200_cpu.or1200_sprs.npc_sel LUT6 I5 In - 6.461 -
  39. or1200_top0.or1200_cpu.or1200_sprs.npc_sel LUT6 O Out 0.061 6.522 -
  40. npc_sel Net - - 0.589 - 54
  41. or1200_top0.or1200_cpu.or1200_ctrl.no_more_dslot_i_a2_1_lut6_2_RNI9FVE1 LUT5 I3 In - 7.111 -
  42. or1200_top0.or1200_cpu.or1200_ctrl.no_more_dslot_i_a2_1_lut6_2_RNI9FVE1 LUT5 O Out 0.122 7.233 -
  43. un1_pc46_0 Net - - 0.585 - 32
  44. or1200_top0.or1200_cpu.or1200_genpc.pcreg_default_RNI5L3L1[2] LUT3 I2 In - 7.818 -
  45. or1200_top0.or1200_cpu.or1200_genpc.pcreg_default_RNI5L3L1[2] LUT3 O Out 0.061 7.879 -
  46. pc_m0_axb_0 Net - - 0.000 - 2
  47. or1200_top0.or1200_cpu.or1200_genpc.pc_m0_cry_0 MUXCY_L S In - 7.879 -
  48. or1200_top0.or1200_cpu.or1200_genpc.pc_m0_cry_0 MUXCY_L LO Out 0.219 8.098 -
  49. pc_m0_cry_0 Net - - 0.000 - 2
  50. or1200_top0.or1200_cpu.or1200_genpc.pc_m0_cry_1 MUXCY_L CI In - 8.098 -
  51. or1200_top0.or1200_cpu.or1200_genpc.pc_m0_cry_1 MUXCY_L LO Out 0.016 8.115 -
  52. pc_m0_cry_1 Net - - 0.000 - 2
  53. or1200_top0.or1200_cpu.or1200_genpc.pc_m0_cry_2 MUXCY_L CI In - 8.115 -
  54. or1200_top0.or1200_cpu.or1200_genpc.pc_m0_cry_2 MUXCY_L LO Out 0.016 8.131 -
  55. pc_m0_cry_2 Net - - 0.000 - 2
  56. or1200_top0.or1200_cpu.or1200_genpc.pc_m0_cry_3 MUXCY_L CI In - 8.131 -
  57. or1200_top0.or1200_cpu.or1200_genpc.pc_m0_cry_3 MUXCY_L LO Out 0.016 8.147 -
  58. pc_m0_cry_3 Net - - 0.000 - 2
  59. or1200_top0.or1200_cpu.or1200_genpc.pc_m0_cry_4 MUXCY_L CI In - 8.147 -
  60. or1200_top0.or1200_cpu.or1200_genpc.pc_m0_cry_4 MUXCY_L LO Out 0.016 8.164 -
  61. pc_m0_cry_4 Net - - 0.000 - 2
  62. or1200_top0.or1200_cpu.or1200_genpc.pc_m0_cry_5 MUXCY_L CI In - 8.164 -
  63. or1200_top0.or1200_cpu.or1200_genpc.pc_m0_cry_5 MUXCY_L LO Out 0.016 8.180 -
  64. pc_m0_cry_5 Net - - 0.000 - 2
  65. or1200_top0.or1200_cpu.or1200_genpc.pc_m0_cry_6 MUXCY_L CI In - 8.180 -
  66. or1200_top0.or1200_cpu.or1200_genpc.pc_m0_cry_6 MUXCY_L LO Out 0.016 8.196 -
  67. pc_m0_cry_6 Net - - 0.000 - 2
  68. or1200_top0.or1200_cpu.or1200_genpc.pc_m0_cry_7 MUXCY_L CI In - 8.196 -
  69. or1200_top0.or1200_cpu.or1200_genpc.pc_m0_cry_7 MUXCY_L LO Out 0.016 8.213 -
  70. pc_m0_cry_7 Net - - 0.000 - 2
  71. or1200_top0.or1200_cpu.or1200_genpc.pc_m0_cry_8 MUXCY_L CI In - 8.213 -
  72. or1200_top0.or1200_cpu.or1200_genpc.pc_m0_cry_8 MUXCY_L LO Out 0.016 8.229 -
  73. pc_m0_cry_8 Net - - 0.000 - 2
  74. or1200_top0.or1200_cpu.or1200_genpc.pc_m0_cry_9 MUXCY_L CI In - 8.229 -
  75. or1200_top0.or1200_cpu.or1200_genpc.pc_m0_cry_9 MUXCY_L LO Out 0.016 8.245 -
  76. pc_m0_cry_9 Net - - 0.000 - 2
  77. or1200_top0.or1200_cpu.or1200_genpc.pc_m0_cry_10 MUXCY_L CI In - 8.245 -
  78. or1200_top0.or1200_cpu.or1200_genpc.pc_m0_cry_10 MUXCY_L LO Out 0.016 8.261 -
  79. pc_m0_cry_10 Net - - 0.000 - 2
  80. or1200_top0.or1200_cpu.or1200_genpc.pc_m0_cry_11 MUXCY_L CI In - 8.261 -
  81. or1200_top0.or1200_cpu.or1200_genpc.pc_m0_cry_11 MUXCY_L LO Out 0.016 8.278 -
  82. pc_m0_cry_11 Net - - 0.000 - 2
  83. or1200_top0.or1200_cpu.or1200_genpc.pc_m0_cry_12 MUXCY_L CI In - 8.278 -
  84. or1200_top0.or1200_cpu.or1200_genpc.pc_m0_cry_12 MUXCY_L LO Out 0.016 8.294 -
  85. pc_m0_cry_12 Net - - 0.000 - 2
  86. or1200_top0.or1200_cpu.or1200_genpc.pc_m0_cry_13 MUXCY_L CI In - 8.294 -
  87. or1200_top0.or1200_cpu.or1200_genpc.pc_m0_cry_13 MUXCY_L LO Out 0.016 8.310 -
  88. pc_m0_cry_13 Net - - 0.000 - 2
  89. or1200_top0.or1200_cpu.or1200_genpc.pc_m0_cry_14 MUXCY_L CI In - 8.310 -
  90. or1200_top0.or1200_cpu.or1200_genpc.pc_m0_cry_14 MUXCY_L LO Out 0.016 8.327 -
  91. pc_m0_cry_14 Net - - 0.000 - 2
  92. or1200_top0.or1200_cpu.or1200_genpc.pc_m0_cry_15 MUXCY_L CI In - 8.327 -
  93. or1200_top0.or1200_cpu.or1200_genpc.pc_m0_cry_15 MUXCY_L LO Out 0.016 8.343 -
  94. pc_m0_cry_15 Net - - 0.000 - 2
  95. or1200_top0.or1200_cpu.or1200_genpc.pc_m0_cry_16 MUXCY_L CI In - 8.343 -
  96. or1200_top0.or1200_cpu.or1200_genpc.pc_m0_cry_16 MUXCY_L LO Out 0.016 8.359 -
  97. pc_m0_cry_16 Net - - 0.000 - 2
  98. or1200_top0.or1200_cpu.or1200_genpc.pc_m0_cry_17 MUXCY_L CI In - 8.359 -
  99. or1200_top0.or1200_cpu.or1200_genpc.pc_m0_cry_17 MUXCY_L LO Out 0.016 8.376 -
  100. pc_m0_cry_17 Net - - 0.000 - 2
  101. or1200_top0.or1200_cpu.or1200_genpc.pc_m0_cry_18 MUXCY_L CI In - 8.376 -
  102. or1200_top0.or1200_cpu.or1200_genpc.pc_m0_cry_18 MUXCY_L LO Out 0.016 8.392 -
  103. pc_m0_cry_18 Net - - 0.000 - 2
  104. or1200_top0.or1200_cpu.or1200_genpc.pc_m0_cry_19 MUXCY_L CI In - 8.392 -
  105. or1200_top0.or1200_cpu.or1200_genpc.pc_m0_cry_19 MUXCY_L LO Out 0.016 8.408 -
  106. pc_m0_cry_19 Net - - 0.000 - 2
  107. or1200_top0.or1200_cpu.or1200_genpc.pc_m0_cry_20 MUXCY_L CI In - 8.408 -
  108. or1200_top0.or1200_cpu.or1200_genpc.pc_m0_cry_20 MUXCY_L LO Out 0.016 8.425 -
  109. pc_m0_cry_20 Net - - 0.000 - 2
  110. or1200_top0.or1200_cpu.or1200_genpc.pc_m0_cry_21 MUXCY_L CI In - 8.425 -
  111. or1200_top0.or1200_cpu.or1200_genpc.pc_m0_cry_21 MUXCY_L LO Out 0.016 8.441 -
  112. pc_m0_cry_21 Net - - 0.000 - 2
  113. or1200_top0.or1200_cpu.or1200_genpc.pc_m0_cry_22 MUXCY_L CI In - 8.441 -
  114. or1200_top0.or1200_cpu.or1200_genpc.pc_m0_cry_22 MUXCY_L LO Out 0.016 8.457 -
  115. pc_m0_cry_22 Net - - 0.000 - 2
  116. or1200_top0.or1200_cpu.or1200_genpc.pc_m0_cry_23 MUXCY_L CI In - 8.457 -
  117. or1200_top0.or1200_cpu.or1200_genpc.pc_m0_cry_23 MUXCY_L LO Out 0.016 8.473 -
  118. pc_m0_cry_23 Net - - 0.000 - 2
  119. or1200_top0.or1200_cpu.or1200_genpc.pc_m0_cry_24 MUXCY_L CI In - 8.473 -
  120. or1200_top0.or1200_cpu.or1200_genpc.pc_m0_cry_24 MUXCY_L LO Out 0.016 8.490 -
  121. pc_m0_cry_24 Net - - 0.000 - 2
  122. or1200_top0.or1200_cpu.or1200_genpc.pc_m0_cry_25 MUXCY_L CI In - 8.490 -
  123. or1200_top0.or1200_cpu.or1200_genpc.pc_m0_cry_25 MUXCY_L LO Out 0.016 8.506 -
  124. pc_m0_cry_25 Net - - 0.000 - 2
  125. or1200_top0.or1200_cpu.or1200_genpc.pc_m0_cry_26 MUXCY_L CI In - 8.506 -
  126. or1200_top0.or1200_cpu.or1200_genpc.pc_m0_cry_26 MUXCY_L LO Out 0.016 8.522 -
  127. pc_m0_cry_26 Net - - 0.000 - 2
  128. or1200_top0.or1200_cpu.or1200_genpc.pc_m0_cry_27 MUXCY_L CI In - 8.522 -
  129. or1200_top0.or1200_cpu.or1200_genpc.pc_m0_cry_27 MUXCY_L LO Out 0.016 8.539 -
  130. pc_m0_cry_27 Net - - 0.000 - 2
  131. or1200_top0.or1200_cpu.or1200_genpc.pc_m0_s_28 XORCY CI In - 8.539 -
  132. or1200_top0.or1200_cpu.or1200_genpc.pc_m0_s_28 XORCY O Out 0.198 8.736 -
  133. pc_m0[30] Net - - 0.263 - 1
  134. or1200_top0.or1200_cpu.or1200_genpc.pc_RNO[30] LUT5_L I4 In - 8.999 -
  135. or1200_top0.or1200_cpu.or1200_genpc.pc_RNO[30] LUT5_L LO Out 0.061 9.060 -
  136. pc_m2[30] Net - - 0.194 - 1
  137. or1200_top0.or1200_cpu.or1200_genpc.pc[30] LUT6 I5 In - 9.254 -
  138. or1200_top0.or1200_cpu.or1200_genpc.pc[30] LUT6 O Out 0.061 9.315 -
  139. pc[30] Net - - 0.336 - 3
  140. or1200_top0.or1200_cpu.or1200_genpc.icpu_adr_o[30] LUT3 I2 In - 9.651 -
  141. or1200_top0.or1200_cpu.or1200_genpc.icpu_adr_o[30] LUT3 O Out 0.061 9.712 -
  142. icpu_adr_cpu[30] Net - - 0.336 - 3
  143. or1200_top0.or1200_immu_top.un2_page_cross_0_I_18 LUT6 I5 In - 10.049 -
  144. or1200_top0.or1200_immu_top.un2_page_cross_0_I_18 LUT6 O Out 0.197 10.246 -
  145. un2_page_cross_0_N_32 Net - - 0.000 - 1
  146. or1200_top0.or1200_immu_top.un2_page_cross_0_I_11 MUXCY S In - 10.246 -
  147. or1200_top0.or1200_immu_top.un2_page_cross_0_I_11 MUXCY O Out 0.219 10.465 -
  148. un2_page_cross_0_data_tmp[5] Net - - 0.000 - 2
  149. or1200_top0.or1200_immu_top.un2_page_cross_0_I_51 MUXCY CI In - 10.465 -
  150. or1200_top0.or1200_immu_top.un2_page_cross_0_I_51 MUXCY O Out 0.016 10.481 -
  151. un2_page_cross_0_I_51 Net - - 0.446 - 10
  152. or1200_top0.or1200_immu_top.fault LUT5 I4 In - 10.927 -
  153. or1200_top0.or1200_immu_top.fault LUT5 O Out 0.061 10.988 -
  154. fault Net - - 0.365 - 4
  155. or1200_top0.or1200_immu_top.icpu_err_o LUT5 I4 In - 11.354 -
  156. or1200_top0.or1200_immu_top.icpu_err_o LUT5 O Out 0.094 11.447 -
  157. icpu_err_o_0 Net - - 0.586 - 38
  158. or1200_top0.or1200_cpu.or1200_freeze.un2_id_freeze LUT4 I3 In - 12.034 -
  159. or1200_top0.or1200_cpu.or1200_freeze.un2_id_freeze LUT4 O Out 0.061 12.095 -
  160. un2_id_freeze Net - - 0.446 - 10
  161. or1200_top0.or1200_cpu.or1200_freeze.wb_freeze_1_i_a2 LUT6 I5 In - 12.541 -
  162. or1200_top0.or1200_cpu.or1200_freeze.wb_freeze_1_i_a2 LUT6 O Out 0.061 12.602 -
  163. waiting_on15 Net - - 0.594 - 84
  164. or1200_top0.or1200_cpu.or1200_except.tick_pending LUT6 I5 In - 13.196 -
  165. or1200_top0.or1200_cpu.or1200_except.tick_pending LUT6 O Out 0.061 13.257 -
  166. tick_pending Net - - 0.446 - 10
  167. or1200_top0.or1200_cpu.or1200_except.un1_except_flushpipe_0_3_RNIPOT18_0 LUT6 I5 In - 13.703 -
  168. or1200_top0.or1200_cpu.or1200_except.un1_except_flushpipe_0_3_RNIPOT18_0 LUT6 O Out 0.144 13.847 -
  169. un1_except_flushpipe_0_1 Net - - 0.592 - 70
  170. or1200_top0.or1200_cpu.or1200_if.if_bypass_reg_RNIEH7IH LUT6 I5 In - 14.439 -
  171. or1200_top0.or1200_cpu.or1200_if.if_bypass_reg_RNIEH7IH LUT6 O Out 0.061 14.500 -
  172. if_insn_sn_N_13 Net - - 0.468 - 13
  173. or1200_top0.or1200_cpu.or1200_if.if_insn_ss0 LUT3 I2 In - 14.968 -
  174. or1200_top0.or1200_cpu.or1200_if.if_insn_ss0 LUT3 O Out 0.061 15.029 -
  175. if_insn_ss0 Net - - 0.578 - 28
  176. or1200_top0.or1200_cpu.or1200_rf.g0_0_0 LUT6_L I5 In - 15.606 -
  177. or1200_top0.or1200_cpu.or1200_rf.g0_0_0 LUT6_L LO Out 0.061 15.667 -
  178. g0_0_0 Net - - 0.194 - 1
  179. or1200_top0.or1200_cpu.or1200_rf.g0_0 LUT6 I5 In - 15.861 -
  180. or1200_top0.or1200_cpu.or1200_rf.g0_0 LUT6 O Out 0.061 15.922 -
  181. un1_rf_ena Net - - 0.307 - 2
  182. or1200_top0.or1200_cpu.or1200_rf.rf_ena_i LUT6 I5 In - 16.229 -
  183. or1200_top0.or1200_cpu.or1200_rf.rf_ena_i LUT6 O Out 0.061 16.290 -
  184. N_45 Net - - 0.380 - 5
  185. or1200_top0.or1200_cpu.or1200_rf.rf_a.addr_a_reg_0[0] LUT6 I5 In - 16.670 -
  186. or1200_top0.or1200_cpu.or1200_rf.rf_a.addr_a_reg_0[0] LUT6 O Out 0.061 16.731 -
  187. addr_a_reg_0[0] Net - - 0.414 - 2
  188. or1200_top0.or1200_cpu.or1200_rf.rf_a.mem_mem_0_0 RAMB36E1 ADDRARDADDR[5] In - 17.145 -
  189. =====================================================================================================================================================
  190. Total path delay (propagation time + setup) of 14.195 is 3.770(26.6%) logic and 10.425(73.4%) route.
  191. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value
  192.  
  193.  
  194. Start clock path:
  195.  
  196. Instance / Net Pin Pin Arrival No. of
  197. Name Type Name Dir Delay Time Fan Out(s)
  198. -------------------------------------------------------------------------------------------------------------------
  199. Start Clock : clk
  200. ------------
  201. clk Port clk In - 0.000 -
  202. clk Net - - 0.000 - 1
  203. clk_ibuf_iso IBUFG I In - 0.000 -
  204. clk_ibuf_iso IBUFG O Out 0.768 0.768 -
  205. clk_ibuf_iso Net - - 0.528 - 1
  206. clk_ibuf BUFG I In - 1.296 -
  207. clk_ibuf BUFG O Out 0.079 1.375 -
  208. or1200_top0.clk_c Net - - 1.985 - 2906
  209. or1200_top0.or1200_cpu.or1200_except.ex_freeze_prev FDC C In - 3.360 -
  210. ===================================================================================================================
  211.  
  212.  
  213. End clock path:
  214.  
  215. Instance / Net Pin Pin Arrival No. of
  216. Name Type Name Dir Delay Time Fan Out(s)
  217. -------------------------------------------------------------------------------------------------------------------------
  218. Start Clock : clk
  219. ------------
  220. clk Port clk In - 0.000 -
  221. clk Net - - 0.000 - 1
  222. clk_ibuf_iso IBUFG I In - 0.000 -
  223. clk_ibuf_iso IBUFG O Out 0.768 0.768 -
  224. clk_ibuf_iso Net - - 0.528 - 1
  225. clk_ibuf BUFG I In - 1.296 -
  226. clk_ibuf BUFG O Out 0.079 1.375 -
  227. or1200_top0.clk_c Net - - 1.985 - 2906
  228. or1200_top0.or1200_cpu.or1200_rf.rf_a.mem_mem_0_0 RAMB36E1 CLKARDCLK In - 3.360 -
  229. =========================================================================================================================
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