signal b :  std_logic_vector(31 downto 0);
    signal e :  std_logic_vector(23 downto 0);
signal right : std_logic_vector((DATA_WIDTH)-1 downto 0);
signal left  :  std_logic_vector((DATA_WIDTH)-1 downto 0);
signal left_shifted  :  std_logic_vector((2*DATA_WIDTH)-1 downto 0);
signal new_right  :  std_logic_vector((2*DATA_WIDTH)-1 downto 0);

a => a(15 downto 0),
**b => b(15 downto 0),**   here is error line 42
c => right

MULTIPLIER_left:entity work.mult16bit

a => a(31 downto 16),
b => b(31 downto 16),
c => left

left_shifted <= left & "00000000000000000000000000000000" ;
    -- left_shifted <= std_logic_vector("sll"(unsigned(left), 8));

     new_right <= "00000000000000000000000000000000" & right;


     c <= unsigned(new_right) + unsigned(left_shifted) ;