licznik

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.all;

entity licznik is
PORT(DIR: in STD_LOGIC;
		clk: in STD_LOGIC;
		carry: out STD_LOGIC;
		Q: buffer STD_LOGIC_VECTOR(3 downto 0));
end licznik;
architecture licz of licznik is
begin

	process(clk)

	begin

if rising_edge (clk) then
carry <= '0';
if DIR='0'
	then Q<=Q+1;
	if Q = "1001" then
	Q <= "0000";
	carry <= '1';

	end if;
	else
	Q<=Q-1;
if Q = "0000" then
	Q <= "1001";
	carry <= '1';
	end if;
	end if;
	end if;
	end process;
	end architecture;