`timescale 1ns / 1ps

module Mux_structural(
    input s0,
    input s1,
    input i0,
    input i1,
    input i2,
    input i3,
    output reg d
    );

    always @(s0, s1, i0, i1, i2, i3)
    begin

    d=1'b0;

        case ({s1,s0,i3,i2,i1,i0})
        4'b000001 : d = 1'b1;
        default: begin
                 d=1'b0;
                 end
        endcase

        case ({s1,s0,i3,i2,i1,i0})
        4'b010010 : d = 1'b1;
        default: begin
                 d=1'b0;
                 end
        endcase

        case ({s1,s0,i3,i2,i1,i0})
        4'b100100 : d = 1'b1;
        default: begin
                 d=1'b0;
                 end
        endcase

        case ({s1,s0,i3,i2,i1,i0})
        4'b111000 : d = 1'b1;
        default: begin
                 d=1'b0;
                 end
        endcase
    end

endmodule