library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity pulse is
generic(N: integer range 0 to 32 := 8);
port (
clk    : in std_logic;
reset  : in std_logic;
trig   : in std_logic;
pulse_len  : in UNSIGNED(N-1 downto 0);
wave   : out std_logic);
end pulse;


architecture rtl of pulse is

type FSM is (CZUWAJ, GENERUJ);

signal stan, stan_nast: FSM;
signal stoper, zapisane_pl: UNSIGNED(N-1 downto 0);
signal zeruj: std_logic;

begin

STATE_REG_PROC:
process (reset, clk)
begin
  if(reset='0') then
    stan <= CZUWAJ;
  elsif(rising_edge(clk)) then
    stan <= stan_nast;

  end if;
end process;


NEXT_STATE_PROC:
process (clk)
begin
    case stan is
     when CZUWAJ =>
       if(trig='1' and not (zapisane_pl =0)) then
         stan_nast<=GENERUJ;
         --zeruj<='0';
         else
           stan_nast<=CZUWAJ;
           zeruj <= '0';
       end if;

       when GENERUJ =>
         if(stoper<zapisane_pl-1) then
           stan_nast <= CZUWAJ;
           zeruj <= '1';
          elsif(trig='1') then
             stan_nast <= CZUWAJ;
             zeruj <='1';
            else
               stan_nast<=GENERUJ;

          end if;



     end case;
end process;


WAVE_PROC:
process (stan)
begin
    case stan is
    when CZUWAJ =>
      wave <= '0';
    when GENERUJ =>
      wave <= '1';

    end case;
end process;

TIMER_PROC:
process (clk,trig)
begin
if (reset = '0' or stan =CZUWAJ or zeruj = '1') then
  stoper <= (others => '0');
elsif (rising_edge(clk)) then
  stoper <= stoper+1;
  end if;

end process;


SAVE_PULSE_LEN_PROC:
process (clk, reset)
begin
  if(rising_edge(clk)) then
    if (pulse_len=0 )then
      zapisane_pl <= to_unsigned(1,N);
  else
    zapisane_pl <=pulse_len;
  end if;
  end if;
end process;

end rtl;