probe-rs v0.25 STM32F429 BMP

$ env RUST_LOG=trace target/debug/probe-rs info --probe 1d50:6018:3586399B3032 --protocol jtag 2>../probe-rs-bmp-stm32f429-jtag.log
Probing target via JTAG

ARM Chip with debug port Default:
Debug Port: DPv0, DP Designer: <unknown>
└── 0 MemoryAP (AmbaAhb3)
    └── Error during access: The selected probe does not support the 'ARM' interface.


RISC-V Chip:
  IDCODE: 0000000000
    Version:      0
    Part:         0
    Manufacturer: 0 (Unknown Manufacturer Code)
Error showing Xtensa chip information: An error originating from the DebugProbe occurred.

Caused by:
    Invalid instruction register access: 30

$ env RUST_LOG=trace target/debug/probe-rs info --probe 1d50:6018:3586399B3032 --protocol swd 2>../probe-rs-bmp-stm32f429-swd.log
Probing target via SWD

ARM Chip with debug port Default:
Debug Port: DPv1, DP Designer: ARM Ltd
└── 0 MemoryAP (AmbaAhb3)
    └── Error during access: The selected probe does not support the 'ARM' interface.


Debugging RISC-V targets over SWD is not supported. For these targets, JTAG is the only supported protocol. RISC-V specific information cannot be printed.
Debugging Xtensa targets over SWD is not supported. For these targets, JTAG is the only supported protocol. Xtensa specific information cannot be printed.