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  1. import rv32i_types::*;
  2.  
  3. module cache #(
  4.     parameter s_offset = 5,
  5.     parameter s_index  = 3,
  6.     parameter s_tag    = 32 - s_offset - s_index,
  7.     parameter s_mask   = 2**s_offset,
  8.     parameter s_line   = 8*s_mask,
  9.     parameter num_sets = 2**s_index
  10. )
  11. (
  12.     input clk,
  13.  
  14.     /* signals to CPU */
  15.     output logic mem_resp,
  16.     output rv32i_word mem_rdata,
  17.     input logic mem_read,
  18.     input logic mem_write,
  19.     input logic [3:0] mem_byte_enable,
  20.     input rv32i_word mem_address,
  21.     input rv32i_word mem_wdata,
  22.    
  23.     /* signals from pmem */
  24.     input logic [255:0] pmem_rdata,
  25.     input logic pmem_resp,
  26.     input logic pmem_address,
  27.     input logic [255:0] pmem_wdata,
  28.     input logic pmem_read,
  29.     input logic pmem_write
  30. );
  31.  
  32. /* datapath and control signals */
  33. logic read_valid_0;
  34. logic read_valid_1;
  35. logic read_dirty_0;
  36. logic read_dirty_1;
  37. logic read_tag_0;
  38. logic read_tag_1;
  39. logic read_data_0;
  40. logic read_data_1;
  41. logic read_LRU;
  42. logic load_valid_0;
  43. logic load_valid_1;
  44. logic load_dirty_0;
  45. logic load_dirty_1;
  46. logic load_tag_0;
  47. logic load_tag_1;
  48. logic load_data_0;
  49. logic load_data_1;
  50. logic load_LRU;
  51. logic dirty_0_val;
  52. logic dirty_1_val;
  53. logic LRU_out;
  54.  
  55. /* bus adapter signals */
  56. logic [255:0] mem_wdata256;
  57. logic [255:0] mem_rdata256;
  58. //logic [31:0] mem_wdata;
  59. //logic [31:0] mem_rdata;
  60. //logic [3:0] mem_byte_enable;
  61. logic [31:0] mem_byte_enable256;
  62. logic [31:0] address;
  63.  
  64. /* instantiating top-level cache blocks */
  65. cache_datapath datapath
  66. (
  67.     .clk,
  68.     .mem_address(mem_address),
  69.     //.mem_wdata(mem_wdata),
  70.     .mem_read(mem_read),
  71.     //.mem_write(mem_write),
  72.     .mem_byte_enable(mem_byte_enable),
  73.     .pmem_rdata(pmem_rdata),
  74.     .pmem_resp(pmem_resp),
  75.     .mem_rdata(mem_rdata),
  76.     .mem_resp(mem_resp),
  77.     //.pmem_address(pmem_address),
  78.     //.pmem_wdata(pmem_wdata),
  79.     //.pmem_read(pmem_read),
  80.     //.pmem_write(pmem_write),
  81.     .read_valid_0(read_valid_0),
  82.    .read_valid_1(read_valid_1),
  83.    .read_dirty_0(read_dirty_0),
  84.    .read_dirty_1(read_dirty_1),
  85.    .read_tag_0(read_tag_0),
  86.    .read_tag_1(read_tag_1),
  87.    .read_data_0(read_data_0),
  88.    .read_data_1(read_data_1),
  89.    .read_LRU(read_LRU),
  90.    .load_valid_0(load_valid_0),
  91.    .load_valid_1(load_valid_1),
  92.    .load_dirty_0(load_dirty_0),
  93.    .load_dirty_1(load_dirty_1),
  94.    .load_tag_0(load_tag_0),
  95.    .load_tag_1(load_tag_1),
  96.    .load_data_0(load_data_0),
  97.    .load_data_1(load_data_1),
  98.    .load_LRU(load_LRU),
  99.    .dirty_0_val(dirty_0_val),
  100.    .dirty_1_val(dirty_1_val),
  101.     .mem_rdata256(mem_rdata256),
  102.     .LRU_out(LRU_out)
  103. );
  104.  
  105. cache_control control
  106. (
  107.     .mem_read(mem_read),
  108.     .mem_write(mem_write),
  109.     .mem_address(mem_address),
  110.     .valid_0_out(valid_0_out),
  111.     .valid_1_out(valid_1_out),
  112.     .tag_0_out(tag_0_out),
  113.     .tag_1_out(tag_1_out),
  114.     .dirty_0_out(dirty_0_out),
  115.     .dirty_1_out(dirty_1_out),
  116.     .pmem_resp(pmem_resp),
  117.     .LRU_out(LRU_out),
  118.     .read_valid_0(read_valid_0),
  119.     .read_valid_1(read_valid_1),
  120.     .read_dirty_0(read_dirty_0),
  121.     .read_dirty_1(read_dirty_1),
  122.     .read_tag_0(read_tag_0),
  123.     .read_tag_1(read_tag_1),
  124.     .read_data_0(read_data_0),
  125.     .read_data_1(read_data_1),
  126.     .read_LRU(read_LRU),
  127.     .load_valid_0(load_valid_0),
  128.     .load_valid_1(load_valid_1),
  129.     .load_dirty_0(load_dirty_0),
  130.     .load_dirty_1(load_dirty_1),
  131.     .load_tag_0(load_tag_0),
  132.     .load_tag_1(load_tag_1),
  133.     .load_data_0(load_data_0),
  134.     .load_data_1(load_data_1),
  135.     .load_LRU(load_LRU)
  136. );
  137.  
  138. bus_adapter bus_adapter
  139. (
  140.     .mem_wdata256(mem_wdata256),
  141.     .mem_rdata256(mem_rdata256),
  142.     .mem_wdata(mem_wdata),
  143.     .mem_rdata(mem_rdata),
  144.     .mem_byte_enable(mem_byte_enable),
  145.     .mem_byte_enable256(mem_byte_enable256),
  146.     .address(address)
  147. );
  148.  
  149. endmodule : cache
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