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  1. # ******************************************************************************
  2.  
  3. # iCEcube Static Timer
  4.  
  5. # Version: 2017.08.27940
  6.  
  7. # Build Date: Sep 12 2017 08:03:55
  8.  
  9. # File Generated: Dec 6 2018 01:01:42
  10.  
  11. # Purpose: Timing Report with critical paths info
  12.  
  13. # Copyright (C) 2006-2010 by Lattice Semiconductor Corp. All rights reserved.
  14.  
  15. # ******************************************************************************
  16.  
  17. Device: iCE40UP5K
  18. Derating factors (Best:Typical:Worst) :- ( 0.491675 : 0.859651 : 1.32445 )
  19. Derating factor used to generate this timing report: Worst
  20. Based on the following operating conditions
  21. Junction Temperature(degree Celsius): 85
  22. Core Voltage(V): 1.14
  23. Process Corner: Worst
  24. NOTE:
  25. Please check both worst-case and best-case scenarios for "Setup Times"
  26. and "Hold Times" checks
  27. #####################################################################
  28. Table of Contents
  29. =====================================================================
  30. 1::Clock Frequency Summary
  31. 2::Clock Relationship Summary
  32. 3::Datasheet Report
  33. 3.1::Setup Times
  34. 3.2::Clock to Out
  35. 3.3::Pad to Pad
  36. 3.4::Hold Times
  37. 3.5::Minimum Clock to Out
  38. 3.6::Minimum Pad To Pad
  39. 4::Path Details for Clock Frequency Summary
  40. 4.1::Critical Path Report for clk_if
  41. 5::Path Details for Clock Relationship Summary
  42. 5.1::Critical Path Report for (clk_if:R vs. clk_if:R)
  43. 6::Path Details for DataSheet
  44. 6.1::Setup Times Path Details
  45. 6.1.1::Path details for port: fx2_fd[0]:in
  46. 6.1.2::Path details for port: fx2_fd[1]:in
  47. 6.1.3::Path details for port: fx2_fd[2]:in
  48. 6.1.4::Path details for port: fx2_fd[3]:in
  49. 6.1.5::Path details for port: fx2_fd[4]:in
  50. 6.1.6::Path details for port: fx2_fd[5]:in
  51. 6.1.7::Path details for port: fx2_fd[6]:in
  52. 6.1.8::Path details for port: fx2_fd[7]:in
  53. 6.1.9::Path details for port: fx2_fifoadr[0]:in
  54. 6.1.10::Path details for port: fx2_fifoadr[1]:in
  55. 6.1.11::Path details for port: fx2_flag[0]:in
  56. 6.1.12::Path details for port: fx2_flag[1]:in
  57. 6.1.13::Path details for port: fx2_flag[2]:in
  58. 6.1.14::Path details for port: fx2_flag[3]:in
  59. 6.1.15::Path details for port: fx2_pktend:in
  60. 6.1.16::Path details for port: fx2_sloe:in
  61. 6.1.17::Path details for port: fx2_slrd:in
  62. 6.1.18::Path details for port: fx2_slwr:in
  63. 6.1.19::Path details for port: i2c_scl:in
  64. 6.1.20::Path details for port: i2c_sda:in
  65. 6.2::Clock to Out Path Details
  66. 6.2.1::Path details for port: fx2_fd[0]:out
  67. 6.2.2::Path details for port: fx2_fd[1]:out
  68. 6.2.3::Path details for port: fx2_fd[2]:out
  69. 6.2.4::Path details for port: fx2_fd[3]:out
  70. 6.2.5::Path details for port: fx2_fd[4]:out
  71. 6.2.6::Path details for port: fx2_fd[5]:out
  72. 6.2.7::Path details for port: fx2_fd[6]:out
  73. 6.2.8::Path details for port: fx2_fd[7]:out
  74. 6.2.9::Path details for port: fx2_fifoadr[0]:out
  75. 6.2.10::Path details for port: fx2_fifoadr[1]:out
  76. 6.2.11::Path details for port: fx2_flag[0]:out
  77. 6.2.12::Path details for port: fx2_flag[1]:out
  78. 6.2.13::Path details for port: fx2_flag[2]:out
  79. 6.2.14::Path details for port: fx2_flag[3]:out
  80. 6.2.15::Path details for port: fx2_pktend:out
  81. 6.2.16::Path details for port: fx2_sloe:out
  82. 6.2.17::Path details for port: fx2_slrd:out
  83. 6.2.18::Path details for port: fx2_slwr:out
  84. 6.2.19::Path details for port: i2c_sda:out
  85. 6.3::PI to PO Path Details
  86. 6.4::Hold Times Path Details
  87. 6.4.1::Path details for port: fx2_fd[0]:in
  88. 6.4.2::Path details for port: fx2_fd[1]:in
  89. 6.4.3::Path details for port: fx2_fd[2]:in
  90. 6.4.4::Path details for port: fx2_fd[3]:in
  91. 6.4.5::Path details for port: fx2_fd[4]:in
  92. 6.4.6::Path details for port: fx2_fd[5]:in
  93. 6.4.7::Path details for port: fx2_fd[6]:in
  94. 6.4.8::Path details for port: fx2_fd[7]:in
  95. 6.4.9::Path details for port: fx2_fifoadr[0]:in
  96. 6.4.10::Path details for port: fx2_fifoadr[1]:in
  97. 6.4.11::Path details for port: fx2_flag[0]:in
  98. 6.4.12::Path details for port: fx2_flag[1]:in
  99. 6.4.13::Path details for port: fx2_flag[2]:in
  100. 6.4.14::Path details for port: fx2_flag[3]:in
  101. 6.4.15::Path details for port: fx2_pktend:in
  102. 6.4.16::Path details for port: fx2_sloe:in
  103. 6.4.17::Path details for port: fx2_slrd:in
  104. 6.4.18::Path details for port: fx2_slwr:in
  105. 6.4.19::Path details for port: i2c_scl:in
  106. 6.4.20::Path details for port: i2c_sda:in
  107. 6.5::Minimum Clock to Out Path Details
  108. 6.5.1::Path details for port: fx2_fd[0]:out
  109. 6.5.2::Path details for port: fx2_fd[1]:out
  110. 6.5.3::Path details for port: fx2_fd[2]:out
  111. 6.5.4::Path details for port: fx2_fd[3]:out
  112. 6.5.5::Path details for port: fx2_fd[4]:out
  113. 6.5.6::Path details for port: fx2_fd[5]:out
  114. 6.5.7::Path details for port: fx2_fd[6]:out
  115. 6.5.8::Path details for port: fx2_fd[7]:out
  116. 6.5.9::Path details for port: fx2_fifoadr[0]:out
  117. 6.5.10::Path details for port: fx2_fifoadr[1]:out
  118. 6.5.11::Path details for port: fx2_flag[0]:out
  119. 6.5.12::Path details for port: fx2_flag[1]:out
  120. 6.5.13::Path details for port: fx2_flag[2]:out
  121. 6.5.14::Path details for port: fx2_flag[3]:out
  122. 6.5.15::Path details for port: fx2_pktend:out
  123. 6.5.16::Path details for port: fx2_sloe:out
  124. 6.5.17::Path details for port: fx2_slrd:out
  125. 6.5.18::Path details for port: fx2_slwr:out
  126. 6.5.19::Path details for port: i2c_sda:out
  127. 6.6::Minimum Pad To Pad Path Details
  128. =====================================================================
  129. End of Table of Contents
  130. #####################################################################
  131.  
  132. #####################################################################
  133. 1::Clock Frequency Summary
  134. =====================================================================
  135. Number of clocks: 1
  136. Clock: clk_if | Frequency: 42.75 MHz | Target: 33.33 MHz |
  137.  
  138. =====================================================================
  139. End of Clock Frequency Summary
  140. #####################################################################
  141.  
  142.  
  143. #####################################################################
  144. 2::Clock Relationship Summary
  145. =====================================================================
  146.  
  147. Launch Clock Capture Clock Constraint(R-R) Slack(R-R) Constraint(R-F) Slack(R-F) Constraint(F-F) Slack(F-F) Constraint(F-R) Slack(F-R)
  148. ------------ ------------- --------------- ---------- --------------- ---------- --------------- ---------- --------------- ----------
  149. clk_if clk_if 30000 6610 N/A N/A N/A N/A N/A N/A
  150.  
  151. =====================================================================
  152. End of Clock Relationship Summary
  153. #####################################################################
  154.  
  155.  
  156. #####################################################################
  157. 3::Datasheet Report
  158.  
  159. All values are in Picoseconds
  160. =====================================================================
  161.  
  162. 3.1::Setup Times
  163. ----------------
  164.  
  165. Data Port Clock Port Setup Times Clock Reference:Phase
  166. ----------------- ---------- ----------- ---------------------
  167. fx2_fd[0]:in clk_if:in -1327 clk_if:R
  168. fx2_fd[1]:in clk_if:in -1327 clk_if:R
  169. fx2_fd[2]:in clk_if:in -1327 clk_if:R
  170. fx2_fd[3]:in clk_if:in -1327 clk_if:R
  171. fx2_fd[4]:in clk_if:in -1327 clk_if:R
  172. fx2_fd[5]:in clk_if:in -1327 clk_if:R
  173. fx2_fd[6]:in clk_if:in -1327 clk_if:R
  174. fx2_fd[7]:in clk_if:in -1327 clk_if:R
  175. fx2_fifoadr[0]:in clk_if:in -1327 clk_if:R
  176. fx2_fifoadr[1]:in clk_if:in -1327 clk_if:R
  177. fx2_flag[0]:in clk_if:in -1327 clk_if:R
  178. fx2_flag[1]:in clk_if:in -1327 clk_if:R
  179. fx2_flag[2]:in clk_if:in -1327 clk_if:R
  180. fx2_flag[3]:in clk_if:in -1327 clk_if:R
  181. fx2_pktend:in clk_if:in -1327 clk_if:R
  182. fx2_sloe:in clk_if:in -1327 clk_if:R
  183. fx2_slrd:in clk_if:in -1327 clk_if:R
  184. fx2_slwr:in clk_if:in -1327 clk_if:R
  185. i2c_scl:in clk_if:in -863 clk_if:R
  186. i2c_sda:in clk_if:in 978 clk_if:R
  187.  
  188.  
  189. 3.2::Clock to Out
  190. -----------------
  191.  
  192. Data Port Clock Port Clock to Out Clock Reference:Phase
  193. ------------------ ---------- ------------ ---------------------
  194. fx2_fd[0]:out clk_if:in 9633 clk_if:R
  195. fx2_fd[1]:out clk_if:in 9633 clk_if:R
  196. fx2_fd[2]:out clk_if:in 9633 clk_if:R
  197. fx2_fd[3]:out clk_if:in 9633 clk_if:R
  198. fx2_fd[4]:out clk_if:in 9633 clk_if:R
  199. fx2_fd[5]:out clk_if:in 9633 clk_if:R
  200. fx2_fd[6]:out clk_if:in 9633 clk_if:R
  201. fx2_fd[7]:out clk_if:in 9633 clk_if:R
  202. fx2_fifoadr[0]:out clk_if:in 9633 clk_if:R
  203. fx2_fifoadr[1]:out clk_if:in 9633 clk_if:R
  204. fx2_flag[0]:out clk_if:in 9633 clk_if:R
  205. fx2_flag[1]:out clk_if:in 9633 clk_if:R
  206. fx2_flag[2]:out clk_if:in 9633 clk_if:R
  207. fx2_flag[3]:out clk_if:in 9633 clk_if:R
  208. fx2_pktend:out clk_if:in 9633 clk_if:R
  209. fx2_sloe:out clk_if:in 9633 clk_if:R
  210. fx2_slrd:out clk_if:in 9633 clk_if:R
  211. fx2_slwr:out clk_if:in 9633 clk_if:R
  212. i2c_sda:out clk_if:in 18717 clk_if:R
  213.  
  214.  
  215. 3.3::Pad to Pad
  216. ---------------
  217.  
  218. Port Name (Input) Port Name (Output) Pad to Pad
  219. ----------------- ------------------ ----------
  220.  
  221.  
  222. 3.4::Hold Times
  223. ---------------
  224.  
  225. Data Port Clock Port Hold Times Clock Reference:Phase
  226. ----------------- ---------- ---------- ---------------------
  227. fx2_fd[0]:in clk_if:in 5560 clk_if:R
  228. fx2_fd[1]:in clk_if:in 5560 clk_if:R
  229. fx2_fd[2]:in clk_if:in 5560 clk_if:R
  230. fx2_fd[3]:in clk_if:in 5560 clk_if:R
  231. fx2_fd[4]:in clk_if:in 5560 clk_if:R
  232. fx2_fd[5]:in clk_if:in 5560 clk_if:R
  233. fx2_fd[6]:in clk_if:in 5560 clk_if:R
  234. fx2_fd[7]:in clk_if:in 5560 clk_if:R
  235. fx2_fifoadr[0]:in clk_if:in 5560 clk_if:R
  236. fx2_fifoadr[1]:in clk_if:in 5560 clk_if:R
  237. fx2_flag[0]:in clk_if:in 5560 clk_if:R
  238. fx2_flag[1]:in clk_if:in 5560 clk_if:R
  239. fx2_flag[2]:in clk_if:in 5560 clk_if:R
  240. fx2_flag[3]:in clk_if:in 5560 clk_if:R
  241. fx2_pktend:in clk_if:in 5560 clk_if:R
  242. fx2_sloe:in clk_if:in 5560 clk_if:R
  243. fx2_slrd:in clk_if:in 5560 clk_if:R
  244. fx2_slwr:in clk_if:in 5560 clk_if:R
  245. i2c_scl:in clk_if:in 1592 clk_if:R
  246. i2c_sda:in clk_if:in 254 clk_if:R
  247.  
  248.  
  249. 3.5::Minimum Clock to Out
  250. -------------------------
  251.  
  252. Data Port Clock Port Minimum Clock to Out Clock Reference:Phase
  253. ------------------ ---------- -------------------- ---------------------
  254. fx2_fd[0]:out clk_if:in 9347 clk_if:R
  255. fx2_fd[1]:out clk_if:in 9347 clk_if:R
  256. fx2_fd[2]:out clk_if:in 9347 clk_if:R
  257. fx2_fd[3]:out clk_if:in 9347 clk_if:R
  258. fx2_fd[4]:out clk_if:in 9347 clk_if:R
  259. fx2_fd[5]:out clk_if:in 9347 clk_if:R
  260. fx2_fd[6]:out clk_if:in 9347 clk_if:R
  261. fx2_fd[7]:out clk_if:in 9347 clk_if:R
  262. fx2_fifoadr[0]:out clk_if:in 9347 clk_if:R
  263. fx2_fifoadr[1]:out clk_if:in 9347 clk_if:R
  264. fx2_flag[0]:out clk_if:in 9347 clk_if:R
  265. fx2_flag[1]:out clk_if:in 9347 clk_if:R
  266. fx2_flag[2]:out clk_if:in 9347 clk_if:R
  267. fx2_flag[3]:out clk_if:in 9347 clk_if:R
  268. fx2_pktend:out clk_if:in 9347 clk_if:R
  269. fx2_sloe:out clk_if:in 9347 clk_if:R
  270. fx2_slrd:out clk_if:in 9347 clk_if:R
  271. fx2_slwr:out clk_if:in 9347 clk_if:R
  272. i2c_sda:out clk_if:in 18014 clk_if:R
  273.  
  274.  
  275. 3.6::Minimum Pad To Pad
  276. -----------------------
  277.  
  278. Port Name (Input) Port Name (Output) Minimum Pad To Pad
  279. ----------------- ------------------ ------------------
  280.  
  281. =====================================================================
  282. End of Datasheet Report
  283. #####################################################################
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