module multT (
    input signed [31:0]M,
    input signed [31:0]Q,
    input MultiCon,
    input clk,
    input reset,
    output reg signed [31:0]hi,
    output reg signed [31:0]lo
);

reg signed [64:0]A;
reg signed [64:0]S;
reg signed [64:0]P;
reg signed [31:0]aux;
integer i;
reg con;

initial begin
    i = 32;
    con = 0;
end

always @ (posedge clk) begin
    if (reset == 1) begin
        A = 65'd0;
        S = 65'd0;
        P = 65'd0;
        aux = 32'd0;
        i = 32;
        con = 0;
    end
    if (MultiCon == 0) begin
        con = 0;
    end
    if (MultiCon == 1) begin
        if (i > 31 && con == 0) begin
            A = {Q, 33'b0};
            aux = ~Q + 1;
            S = {aux, 33'b0};
            P = {32'b0, M, 1'b0};
            i = 0;
        end
    end
    if (i < 32) begin
        case (P[1:0])
        2'b01: begin
            P = P + A;
        end
        2'b10: begin
            P = P + S;
        end
        endcase
        P = P >>> 1;
        i = i + 1;
        //hi = i;
        if (i == 32) begin
            hi = P[64:33];
            lo = P[32:1];
            con = 1;
        end
    end
end

endmodule //