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bbai-mcspi2.dts

zmatt
Jul 10th, 2020 (edited)
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  1. // NOTE: this example is not compatible with the new branches that have overlays-support
  2.  
  3. #include "am5729-beagleboneai.dts"
  4. #include "bbai-pins.h"  // https://pastebin.com/vwn4m7Nf
  5.  
  6. &{/chosen} {
  7.     base_dtb = "bbai-mcspi2";   // <-- name of this file goes here
  8. };
  9.  
  10. &{/aliases} {
  11.     // these ought to be in dra7.dtsi but they're missing.
  12.     // they assign spi bus numbers to the spi controller devices.
  13.     // note that dra7.dtsi assigns spi0 to be &qspi.
  14.     spi1 = &mcspi1;
  15.     spi2 = &mcspi2;
  16.     spi3 = &mcspi3;
  17.     spi4 = &mcspi4;
  18. };
  19.  
  20.  
  21. &dra7_pmx_core {
  22.     mcspi2_pins: mcspi2 {
  23.         pinctrl-single,pins = <
  24.             // McSPI clock pin _must_ be configured as PIN_INPUT or the peripheral will not work.
  25.             // ("PIN_INPUT" means input-enabled while "PIN_OUTPUT" means input-disabled.  It has no
  26.             // influence on output-enable, which is controlled by the peripheral it's muxed to.)
  27.             DRA7XX_CORE_IOPAD( P9_22B, PIN_INPUT_PULLUP  | MUX_MODE0  ) // clock
  28.             DRA7XX_CORE_IOPAD( P9_21B, PIN_INPUT_PULLUP  | MUX_MODE0  ) // d1 / data in (miso)
  29.             DRA7XX_CORE_IOPAD( P9_18A, PIN_OUTPUT_PULLUP | MUX_MODE0  ) // d0 / data out (mosi)
  30.             DRA7XX_CORE_IOPAD( P9_17A, PIN_OUTPUT_PULLUP | MUX_MODE0  ) // cs 0
  31.  
  32.             // A/B pairs indicate two processor pins connecting to the same expansion header pin.
  33.             // It's a good idea to always claim both processor pins for any expansion header pin
  34.             // you use.  For the unused processor pin use either PIN_OUTPUT | MUX_MODE15 to
  35.             // disable the pin, or if the pin supports gpio mode you could select that using
  36.             // PIN_INPUT | MUX_MODE14 to be able to monitor the pin.
  37.             DRA7XX_CORE_IOPAD( P9_22A, PIN_OUTPUT        | MUX_MODE15 )
  38.             DRA7XX_CORE_IOPAD( P9_21A, PIN_OUTPUT        | MUX_MODE15 )
  39.             DRA7XX_CORE_IOPAD( P9_18B, PIN_OUTPUT        | MUX_MODE15 )
  40.             DRA7XX_CORE_IOPAD( P9_17B, PIN_OUTPUT        | MUX_MODE15 )
  41.         >;
  42.     };
  43. };
  44.  
  45. &mcspi2 {
  46.     status = "okay";
  47.  
  48.     pinctrl-names = "default";
  49.     pinctrl-0 = <&mcspi2_pins>;
  50.  
  51.     ti,spi-num-cs = <2>;  // number of chip selects used
  52.  
  53.     channel@0 {
  54.         reg = <0>;
  55.         compatible = "spidev";
  56.  
  57.         symlink = "spi/2.0";   // create symlink at /dev/spi/2.0
  58.  
  59.         // FIXME - replace by actual max frequency of device
  60.         spi-max-frequency = <48000000>;
  61.  
  62.         // defaults to SPI mode 0
  63.     };
  64.  
  65.     channel@1 {
  66.         reg = <1>;
  67.         compatible = "spidev";
  68.  
  69.         symlink = "spi/2.1";   // create symlink at /dev/spi/2.1
  70.  
  71.         // FIXME - replace by actual max frequency of device
  72.         spi-max-frequency = <48000000>;
  73.  
  74.         // EXAMPLE - this selects SPI mode 3 (unless overridden by userspace)
  75.         spi-cpol;
  76.         spi-cpha;
  77.     };
  78. };
  79.  
  80.  
  81. // Here's the obnoxious part: since u-boot doesn't have sane pin defaults yet, all pins not  
  82. // explicitly setup above should be overridden here.  This will eventually no longer be needed.  
  83. &cape_pins_default {
  84.     pinctrl-single,pins = <
  85.         DRA7XX_CORE_IOPAD( P9_11A, PIN_INPUT_PULLDOWN | MUX_MODE15 )  // note: has no gpio
  86.         DRA7XX_CORE_IOPAD( P9_11B, PIN_INPUT          | MUX_MODE14 )
  87.         DRA7XX_CORE_IOPAD( P9_12,  PIN_INPUT_PULLDOWN | MUX_MODE14 )
  88.         DRA7XX_CORE_IOPAD( P9_13,  PIN_INPUT_PULLDOWN | MUX_MODE15 )  // note: has no gpio
  89.         DRA7XX_CORE_IOPAD( P9_14,  PIN_INPUT_PULLDOWN | MUX_MODE14 )
  90.         DRA7XX_CORE_IOPAD( P9_15,  PIN_INPUT_PULLDOWN | MUX_MODE14 )
  91.         DRA7XX_CORE_IOPAD( P9_16,  PIN_INPUT_PULLDOWN | MUX_MODE14 )
  92.     //  DRA7XX_CORE_IOPAD( P9_17A, PIN_INPUT_PULLDOWN | MUX_MODE14 )
  93.     //  DRA7XX_CORE_IOPAD( P9_17B, PIN_INPUT          | MUX_MODE14 )
  94.     //  DRA7XX_CORE_IOPAD( P9_18A, PIN_INPUT_PULLDOWN | MUX_MODE14 )
  95.     //  DRA7XX_CORE_IOPAD( P9_18B, PIN_INPUT          | MUX_MODE14 )
  96.         DRA7XX_CORE_IOPAD( P9_19A, PIN_INPUT_PULLUP   | MUX_MODE14 )
  97.         DRA7XX_CORE_IOPAD( P9_19B, PIN_INPUT          | MUX_MODE14 )
  98.         DRA7XX_CORE_IOPAD( P9_20A, PIN_INPUT_PULLUP   | MUX_MODE14 )
  99.         DRA7XX_CORE_IOPAD( P9_20B, PIN_INPUT          | MUX_MODE14 )
  100.     //  DRA7XX_CORE_IOPAD( P9_21A, PIN_INPUT_PULLDOWN | MUX_MODE14 )
  101.     //  DRA7XX_CORE_IOPAD( P9_21B, PIN_INPUT          | MUX_MODE14 )
  102.     //  DRA7XX_CORE_IOPAD( P9_22A, PIN_INPUT_PULLDOWN | MUX_MODE14 )
  103.     //  DRA7XX_CORE_IOPAD( P9_22B, PIN_INPUT          | MUX_MODE14 )
  104.         DRA7XX_CORE_IOPAD( P9_23,  PIN_INPUT_PULLUP   | MUX_MODE14 )
  105.         DRA7XX_CORE_IOPAD( P9_24,  PIN_INPUT_PULLUP   | MUX_MODE14 )
  106.         DRA7XX_CORE_IOPAD( P9_25,  PIN_INPUT_PULLDOWN | MUX_MODE14 )
  107.         DRA7XX_CORE_IOPAD( P9_26A, PIN_INPUT_PULLUP   | MUX_MODE14 )
  108.         DRA7XX_CORE_IOPAD( P9_26B, PIN_INPUT          | MUX_MODE14 )
  109.         DRA7XX_CORE_IOPAD( P9_27A, PIN_INPUT_PULLDOWN | MUX_MODE14 )
  110.         DRA7XX_CORE_IOPAD( P9_27B, PIN_INPUT          | MUX_MODE14 )
  111.         DRA7XX_CORE_IOPAD( P9_28,  PIN_INPUT_PULLDOWN | MUX_MODE14 )
  112.         DRA7XX_CORE_IOPAD( P9_29A, PIN_INPUT_PULLDOWN | MUX_MODE14 )
  113.         DRA7XX_CORE_IOPAD( P9_29B, PIN_INPUT          | MUX_MODE14 )
  114.         DRA7XX_CORE_IOPAD( P9_30,  PIN_INPUT_PULLDOWN | MUX_MODE14 )
  115.         DRA7XX_CORE_IOPAD( P9_31A, PIN_INPUT_PULLDOWN | MUX_MODE14 )
  116.         DRA7XX_CORE_IOPAD( P9_31B, PIN_INPUT          | MUX_MODE14 )
  117.         DRA7XX_CORE_IOPAD( P9_41A, PIN_INPUT_PULLDOWN | MUX_MODE14 )
  118.         DRA7XX_CORE_IOPAD( P9_41B, PIN_INPUT          | MUX_MODE14 )
  119.         DRA7XX_CORE_IOPAD( P9_42A, PIN_INPUT_PULLDOWN | MUX_MODE14 )
  120.         DRA7XX_CORE_IOPAD( P9_42B, PIN_INPUT          | MUX_MODE14 )
  121.         DRA7XX_CORE_IOPAD( P8_03,  PIN_INPUT_PULLUP   | MUX_MODE14 )
  122.         DRA7XX_CORE_IOPAD( P8_04,  PIN_INPUT_PULLUP   | MUX_MODE14 )
  123.         DRA7XX_CORE_IOPAD( P8_05,  PIN_INPUT_PULLUP   | MUX_MODE14 )
  124.         DRA7XX_CORE_IOPAD( P8_06,  PIN_INPUT_PULLUP   | MUX_MODE14 )
  125.         DRA7XX_CORE_IOPAD( P8_07,  PIN_INPUT_PULLDOWN | MUX_MODE14 )
  126.         DRA7XX_CORE_IOPAD( P8_08,  PIN_INPUT_PULLDOWN | MUX_MODE14 )
  127.         DRA7XX_CORE_IOPAD( P8_09,  PIN_INPUT_PULLDOWN | MUX_MODE14 )
  128.         DRA7XX_CORE_IOPAD( P8_10,  PIN_INPUT_PULLDOWN | MUX_MODE14 )
  129.         DRA7XX_CORE_IOPAD( P8_11,  PIN_INPUT_PULLDOWN | MUX_MODE14 )
  130.         DRA7XX_CORE_IOPAD( P8_12,  PIN_INPUT_PULLDOWN | MUX_MODE14 )
  131.         DRA7XX_CORE_IOPAD( P8_13,  PIN_INPUT_PULLDOWN | MUX_MODE14 )
  132.         DRA7XX_CORE_IOPAD( P8_14,  PIN_INPUT_PULLDOWN | MUX_MODE14 )
  133.         DRA7XX_CORE_IOPAD( P8_15A, PIN_INPUT_PULLDOWN | MUX_MODE14 )
  134.         DRA7XX_CORE_IOPAD( P8_15B, PIN_INPUT          | MUX_MODE14 )
  135.         DRA7XX_CORE_IOPAD( P8_16,  PIN_INPUT_PULLDOWN | MUX_MODE14 )
  136.         DRA7XX_CORE_IOPAD( P8_17,  PIN_INPUT_PULLDOWN | MUX_MODE14 )
  137.         DRA7XX_CORE_IOPAD( P8_18,  PIN_INPUT_PULLDOWN | MUX_MODE14 )
  138.         DRA7XX_CORE_IOPAD( P8_19,  PIN_INPUT_PULLDOWN | MUX_MODE14 )
  139.         DRA7XX_CORE_IOPAD( P8_20,  PIN_INPUT_PULLUP   | MUX_MODE14 )
  140.         DRA7XX_CORE_IOPAD( P8_21,  PIN_INPUT_PULLUP   | MUX_MODE14 )
  141.         DRA7XX_CORE_IOPAD( P8_22,  PIN_INPUT_PULLUP   | MUX_MODE14 )
  142.         DRA7XX_CORE_IOPAD( P8_23,  PIN_INPUT_PULLUP   | MUX_MODE14 )
  143.         DRA7XX_CORE_IOPAD( P8_24,  PIN_INPUT_PULLUP   | MUX_MODE14 )
  144.         DRA7XX_CORE_IOPAD( P8_25,  PIN_INPUT_PULLUP   | MUX_MODE14 )
  145.         DRA7XX_CORE_IOPAD( P8_26,  PIN_INPUT_PULLDOWN | MUX_MODE14 )
  146.         DRA7XX_CORE_IOPAD( P8_27A, PIN_INPUT_PULLDOWN | MUX_MODE14 )
  147.         DRA7XX_CORE_IOPAD( P8_27B, PIN_INPUT          | MUX_MODE14 )
  148.         DRA7XX_CORE_IOPAD( P8_28A, PIN_INPUT_PULLDOWN | MUX_MODE14 )
  149.         DRA7XX_CORE_IOPAD( P8_28B, PIN_INPUT          | MUX_MODE14 )
  150.         DRA7XX_CORE_IOPAD( P8_29A, PIN_INPUT_PULLDOWN | MUX_MODE14 )
  151.         DRA7XX_CORE_IOPAD( P8_29B, PIN_INPUT          | MUX_MODE14 )
  152.         DRA7XX_CORE_IOPAD( P8_30A, PIN_INPUT_PULLDOWN | MUX_MODE14 )
  153.         DRA7XX_CORE_IOPAD( P8_30B, PIN_INPUT          | MUX_MODE14 )
  154.         DRA7XX_CORE_IOPAD( P8_31A, PIN_INPUT_PULLDOWN | MUX_MODE14 )
  155.         DRA7XX_CORE_IOPAD( P8_31B, PIN_INPUT_PULLDOWN | MUX_MODE15 )  // note: has no gpio
  156.         DRA7XX_CORE_IOPAD( P8_32A, PIN_INPUT_PULLDOWN | MUX_MODE14 )
  157.         DRA7XX_CORE_IOPAD( P8_32B, PIN_INPUT_PULLDOWN | MUX_MODE15 )  // note: has no gpio
  158.         DRA7XX_CORE_IOPAD( P8_33A, PIN_INPUT_PULLDOWN | MUX_MODE14 )
  159.         DRA7XX_CORE_IOPAD( P8_33B, PIN_INPUT          | MUX_MODE14 )
  160.         DRA7XX_CORE_IOPAD( P8_34A, PIN_INPUT_PULLDOWN | MUX_MODE14 )
  161.         DRA7XX_CORE_IOPAD( P8_34B, PIN_INPUT          | MUX_MODE14 )
  162.         DRA7XX_CORE_IOPAD( P8_35A, PIN_INPUT_PULLDOWN | MUX_MODE14 )
  163.         DRA7XX_CORE_IOPAD( P8_35B, PIN_INPUT          | MUX_MODE14 )
  164.         DRA7XX_CORE_IOPAD( P8_36A, PIN_INPUT_PULLDOWN | MUX_MODE14 )
  165.         DRA7XX_CORE_IOPAD( P8_36B, PIN_INPUT          | MUX_MODE14 )
  166.         DRA7XX_CORE_IOPAD( P8_37A, PIN_INPUT_PULLDOWN | MUX_MODE14 )
  167.         DRA7XX_CORE_IOPAD( P8_37B, PIN_INPUT_PULLDOWN | MUX_MODE15 )  // note: has no gpio
  168.         DRA7XX_CORE_IOPAD( P8_38A, PIN_INPUT_PULLDOWN | MUX_MODE14 )
  169.         DRA7XX_CORE_IOPAD( P8_38B, PIN_INPUT_PULLDOWN | MUX_MODE15 )  // note: has no gpio
  170.         DRA7XX_CORE_IOPAD( P8_39,  PIN_INPUT_PULLDOWN | MUX_MODE14 )
  171.         DRA7XX_CORE_IOPAD( P8_40,  PIN_INPUT_PULLDOWN | MUX_MODE14 )
  172.         DRA7XX_CORE_IOPAD( P8_41,  PIN_INPUT_PULLDOWN | MUX_MODE14 )
  173.         DRA7XX_CORE_IOPAD( P8_42,  PIN_INPUT_PULLDOWN | MUX_MODE14 )
  174.         DRA7XX_CORE_IOPAD( P8_43,  PIN_INPUT_PULLDOWN | MUX_MODE14 )
  175.         DRA7XX_CORE_IOPAD( P8_44,  PIN_INPUT_PULLDOWN | MUX_MODE14 )
  176.         DRA7XX_CORE_IOPAD( P8_45A, PIN_INPUT_PULLDOWN | MUX_MODE14 )
  177.         DRA7XX_CORE_IOPAD( P8_45B, PIN_INPUT          | MUX_MODE14 )
  178.         DRA7XX_CORE_IOPAD( P8_46A, PIN_INPUT_PULLDOWN | MUX_MODE14 )
  179.         DRA7XX_CORE_IOPAD( P8_46B, PIN_INPUT          | MUX_MODE14 )
  180.     >;
  181. };
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