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  1. /*
  2. * arch/arm/mach-tegra/common.c
  3. *
  4. * Copyright (C) 2010 Google, Inc.
  5. * Copyright (C) 2010-2012 NVIDIA Corporation
  6. *
  7. * Author:
  8. * Colin Cross <ccross@android.com>
  9. *
  10. * This software is licensed under the terms of the GNU General Public
  11. * License version 2, as published by the Free Software Foundation, and
  12. * may be copied, distributed, and modified under those terms.
  13. *
  14. * This program is distributed in the hope that it will be useful,
  15. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17. * GNU General Public License for more details.
  18. *
  19. */
  20.  
  21. #include <linux/platform_device.h>
  22. #include <linux/console.h>
  23. #include <linux/init.h>
  24. #include <linux/io.h>
  25. #include <linux/clk.h>
  26. #include <linux/delay.h>
  27. #include <linux/highmem.h>
  28. #include <linux/memblock.h>
  29. #include <linux/bitops.h>
  30. #include <linux/sched.h>
  31. #include <linux/cpufreq.h>
  32.  
  33. #include <asm/hardware/cache-l2x0.h>
  34. #include <asm/system.h>
  35.  
  36. #include <mach/gpio.h>
  37. #include <mach/iomap.h>
  38. #include <mach/pinmux.h>
  39. #include <mach/powergate.h>
  40. #include <mach/system.h>
  41. #include <mach/tegra_smmu.h>
  42.  
  43. #include "apbio.h"
  44. #include "board.h"
  45. #include "clock.h"
  46. #include "fuse.h"
  47. #include "pm.h"
  48. #include "reset.h"
  49. #include "devices.h"
  50.  
  51. #define MC_SECURITY_CFG2 0x7c
  52.  
  53. #define AHB_ARBITRATION_PRIORITY_CTRL 0x4
  54. #define AHB_PRIORITY_WEIGHT(x) (((x) & 0x7) << 29)
  55. #define PRIORITY_SELECT_USB BIT(6)
  56. #define PRIORITY_SELECT_USB2 BIT(18)
  57. #define PRIORITY_SELECT_USB3 BIT(17)
  58.  
  59. #define AHB_GIZMO_AHB_MEM 0xc
  60. #define ENB_FAST_REARBITRATE BIT(2)
  61. #define DONT_SPLIT_AHB_WR BIT(7)
  62.  
  63. #define RECOVERY_MODE BIT(31)
  64. #define BOOTLOADER_MODE BIT(30)
  65. #define FORCED_RECOVERY_MODE BIT(1)
  66.  
  67. #define AHB_GIZMO_USB 0x1c
  68. #define AHB_GIZMO_USB2 0x78
  69. #define AHB_GIZMO_USB3 0x7c
  70. #define IMMEDIATE BIT(18)
  71.  
  72. #define AHB_MEM_PREFETCH_CFG3 0xe0
  73. #define AHB_MEM_PREFETCH_CFG4 0xe4
  74. #define AHB_MEM_PREFETCH_CFG1 0xec
  75. #define AHB_MEM_PREFETCH_CFG2 0xf0
  76. #define PREFETCH_ENB BIT(31)
  77. #define MST_ID(x) (((x) & 0x1f) << 26)
  78. #define AHBDMA_MST_ID MST_ID(5)
  79. #define USB_MST_ID MST_ID(6)
  80. #define USB2_MST_ID MST_ID(18)
  81. #define USB3_MST_ID MST_ID(17)
  82. #define ADDR_BNDRY(x) (((x) & 0xf) << 21)
  83. #define INACTIVITY_TIMEOUT(x) (((x) & 0xffff) << 0)
  84.  
  85. unsigned long tegra_bootloader_fb_start;
  86. unsigned long tegra_bootloader_fb_size;
  87. unsigned long tegra_fb_start;
  88. unsigned long tegra_fb_size;
  89. unsigned long tegra_fb2_start;
  90. unsigned long tegra_fb2_size;
  91. unsigned long tegra_carveout_start;
  92. unsigned long tegra_carveout_size;
  93. unsigned long tegra_vpr_start;
  94. unsigned long tegra_vpr_size;
  95. unsigned long tegra_lp0_vec_start;
  96. unsigned long tegra_lp0_vec_size;
  97. bool tegra_lp0_vec_relocate;
  98. unsigned long tegra_grhost_aperture = ~0ul;
  99. static bool is_tegra_debug_uart_hsport;
  100. static struct board_info pmu_board_info;
  101. static struct board_info display_board_info;
  102. static struct board_info camera_board_info;
  103.  
  104. #ifndef CONFIG_TEGRA_ENABLE_OC
  105. static int pmu_core_edp = 1200; /* default 1.2V EDP limit */
  106. #else
  107. static int pmu_core_edp = 1400; /* default 1.4V EDP limit */
  108. #endif
  109.  
  110. static int board_panel_type;
  111. static enum power_supply_type pow_supply_type = POWER_SUPPLY_TYPE_MAINS;
  112.  
  113. void (*arch_reset)(char mode, const char *cmd) = tegra_assert_system_reset;
  114.  
  115. #define NEVER_RESET 0
  116.  
  117. void tegra_assert_system_reset(char mode, const char *cmd)
  118. {
  119. #if defined(CONFIG_TEGRA_FPGA_PLATFORM) || NEVER_RESET
  120. printk("tegra_assert_system_reset() ignored.....");
  121. do { } while (1);
  122. #else
  123. void __iomem *reset = IO_ADDRESS(TEGRA_PMC_BASE + 0x00);
  124. u32 reg;
  125.  
  126. reg = readl_relaxed(reset + PMC_SCRATCH0);
  127. /* Writing recovery kernel or Bootloader mode in SCRATCH0 31:30:1 */
  128. if (cmd) {
  129. if (!strcmp(cmd, "recovery"))
  130. reg |= RECOVERY_MODE;
  131. else if (!strcmp(cmd, "bootloader"))
  132. reg |= BOOTLOADER_MODE;
  133. else if (!strcmp(cmd, "forced-recovery"))
  134. reg |= FORCED_RECOVERY_MODE;
  135. else
  136. reg &= ~(BOOTLOADER_MODE | RECOVERY_MODE | FORCED_RECOVERY_MODE);
  137. }
  138. else {
  139. /* Clearing SCRATCH0 31:30:1 on default reboot */
  140. reg &= ~(BOOTLOADER_MODE | RECOVERY_MODE | FORCED_RECOVERY_MODE);
  141. }
  142. writel_relaxed(reg, reset + PMC_SCRATCH0);
  143. /* use *_related to avoid spinlock since caches are off */
  144. reg = readl_relaxed(reset);
  145. reg |= 0x10;
  146. writel_relaxed(reg, reset);
  147. #endif
  148. }
  149. static int modem_id;
  150. static int commchip_id;
  151. static int sku_override;
  152. static int debug_uart_port_id;
  153. static enum audio_codec_type audio_codec_name;
  154. static enum image_type board_image_type = system_image;
  155. static int max_cpu_current;
  156.  
  157. /* WARNING: There is implicit client of pllp_out3 like i2c, uart, dsi
  158. * and so this clock (pllp_out3) should never be disabled.
  159. */
  160. static __initdata struct tegra_clk_init_table common_clk_init_table[] = {
  161. /* name parent rate enabled */
  162. { "clk_m", NULL, 0, true },
  163. { "emc", NULL, 0, true },
  164. { "cpu", NULL, 0, true },
  165. { "kfuse", NULL, 0, true },
  166. { "fuse", NULL, 0, true },
  167. { "sclk", NULL, 0, true },
  168. #ifdef CONFIG_TEGRA_SILICON_PLATFORM
  169. #ifdef CONFIG_ARCH_TEGRA_2x_SOC
  170. { "pll_p", NULL, 216000000, true },
  171. { "pll_p_out1", "pll_p", 28800000, true },
  172. { "pll_p_out2", "pll_p", 48000000, false },
  173. { "pll_p_out3", "pll_p", 72000000, true },
  174. { "pll_p_out4", "pll_p", 108000000, false },
  175. { "pll_m", "clk_m", 0, true },
  176. { "pll_m_out1", "pll_m", 120000000, true },
  177. { "sclk", "pll_c_out1", 40000000, true },
  178. { "hclk", "sclk", 40000000, true },
  179. { "pclk", "hclk", 40000000, true },
  180. { "mpe", "pll_c", 0, false },
  181. { "epp", "pll_c", 0, false },
  182. { "vi_sensor", "pll_c", 0, false },
  183. { "vi", "pll_c", 0, false },
  184. { "2d", "pll_c", 0, false },
  185. { "3d", "pll_c", 0, false },
  186. #else
  187. { "pll_p", NULL, 0, true },
  188. { "pll_p_out1", "pll_p", 0, false },
  189. { "pll_p_out2", "pll_p", 48000000, false },
  190. { "pll_p_out3", "pll_p", 0, true },
  191. { "pll_m_out1", "pll_m", 275000000, false },
  192. { "pll_p_out4", "pll_p", 102000000, true },
  193. { "sclk", "pll_p_out4", 102000000, true },
  194. { "hclk", "sclk", 102000000, true },
  195. { "pclk", "hclk", 51000000, true },
  196. #endif
  197. #else
  198. { "pll_p", NULL, 216000000, true },
  199. { "pll_p_out1", "pll_p", 28800000, false },
  200. { "pll_p_out2", "pll_p", 48000000, false },
  201. { "pll_p_out3", "pll_p", 72000000, true },
  202. { "pll_m_out1", "pll_m", 275000000, true },
  203. { "pll_p_out4", "pll_p", 108000000, false },
  204. { "sclk", "pll_p_out4", 108000000, true },
  205. { "hclk", "sclk", 108000000, true },
  206. { "pclk", "hclk", 54000000, true },
  207. #endif
  208. #ifdef CONFIG_TEGRA_SLOW_CSITE
  209. { "csite", "clk_m", 1000000, true },
  210. #else
  211. { "csite", NULL, 0, true },
  212. #endif
  213. { "pll_u", NULL, 480000000, false },
  214. { "sdmmc1", "pll_p", 48000000, false},
  215. { "sdmmc3", "pll_p", 48000000, false},
  216. { "sdmmc4", "pll_p", 48000000, false},
  217. { "sbc1.sclk", NULL, 40000000, false},
  218. { "sbc2.sclk", NULL, 40000000, false},
  219. { "sbc3.sclk", NULL, 40000000, false},
  220. { "sbc4.sclk", NULL, 40000000, false},
  221. #ifndef CONFIG_ARCH_TEGRA_2x_SOC
  222. { "sbc5.sclk", NULL, 40000000, false},
  223. { "sbc6.sclk", NULL, 40000000, false},
  224. { "wake.sclk", NULL, 40000000, true },
  225. { "cbus", "pll_c", 416000000, false },
  226. { "pll_c_out1", "pll_c", 208000000, false },
  227. { "mselect", "pll_p", 102000000, true },
  228. #endif
  229. { NULL, NULL, 0, 0},
  230. };
  231.  
  232. #ifdef CONFIG_CACHE_L2X0
  233. #ifdef CONFIG_TRUSTED_FOUNDATIONS
  234. static void tegra_cache_smc(bool enable, u32 arg)
  235. {
  236. void __iomem *p = IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x3000;
  237. bool need_affinity_switch;
  238. bool can_switch_affinity;
  239. bool l2x0_enabled;
  240. cpumask_t local_cpu_mask;
  241. cpumask_t saved_cpu_mask;
  242. unsigned long flags;
  243. long ret;
  244.  
  245. /*
  246. * ISSUE : Some registers of PL310 controler must be written
  247. * from Secure context (and from CPU0)!
  248. *
  249. * When called form Normal we obtain an abort or do nothing.
  250. * Instructions that must be called in Secure:
  251. * - Write to Control register (L2X0_CTRL==0x100)
  252. * - Write in Auxiliary controler (L2X0_AUX_CTRL==0x104)
  253. * - Invalidate all entries (L2X0_INV_WAY==0x77C),
  254. * mandatory at boot time.
  255. * - Tag and Data RAM Latency Control Registers
  256. * (0x108 & 0x10C) must be written in Secure.
  257. */
  258. need_affinity_switch = (smp_processor_id() != 0);
  259. can_switch_affinity = !irqs_disabled();
  260.  
  261. WARN_ON(need_affinity_switch && !can_switch_affinity);
  262. if (need_affinity_switch && can_switch_affinity) {
  263. cpu_set(0, local_cpu_mask);
  264. sched_getaffinity(0, &saved_cpu_mask);
  265. ret = sched_setaffinity(0, &local_cpu_mask);
  266. WARN_ON(ret != 0);
  267. }
  268.  
  269. local_irq_save(flags);
  270. l2x0_enabled = readl_relaxed(p + L2X0_CTRL) & 1;
  271. if (enable && !l2x0_enabled)
  272. tegra_generic_smc(0xFFFFF100, 0x00000001, arg);
  273. else if (!enable && l2x0_enabled)
  274. tegra_generic_smc(0xFFFFF100, 0x00000002, arg);
  275. local_irq_restore(flags);
  276.  
  277. if (need_affinity_switch && can_switch_affinity) {
  278. ret = sched_setaffinity(0, &saved_cpu_mask);
  279. WARN_ON(ret != 0);
  280. }
  281. }
  282.  
  283. static void tegra_l2x0_disable(void)
  284. {
  285. unsigned long flags;
  286. static u32 l2x0_way_mask;
  287.  
  288. if (!l2x0_way_mask) {
  289. void __iomem *p = IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x3000;
  290. u32 aux_ctrl;
  291. u32 ways;
  292.  
  293. aux_ctrl = readl_relaxed(p + L2X0_AUX_CTRL);
  294. ways = (aux_ctrl & (1 << 16)) ? 16 : 8;
  295. l2x0_way_mask = (1 << ways) - 1;
  296. }
  297.  
  298. local_irq_save(flags);
  299. tegra_cache_smc(false, l2x0_way_mask);
  300. local_irq_restore(flags);
  301. }
  302. #endif /* CONFIG_TRUSTED_FOUNDATIONS */
  303.  
  304. void tegra_init_cache(bool init)
  305. {
  306. void __iomem *p = IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x3000;
  307. u32 aux_ctrl;
  308.  
  309. #ifdef CONFIG_TRUSTED_FOUNDATIONS
  310. /* issue the SMC to enable the L2 */
  311. aux_ctrl = readl_relaxed(p + L2X0_AUX_CTRL);
  312. tegra_cache_smc(true, aux_ctrl);
  313.  
  314. /* after init, reread aux_ctrl and register handlers */
  315. aux_ctrl = readl_relaxed(p + L2X0_AUX_CTRL);
  316. l2x0_init(p, aux_ctrl, 0xFFFFFFFF);
  317.  
  318. /* override outer_disable() with our disable */
  319. outer_cache.disable = tegra_l2x0_disable;
  320. #else
  321. #if defined(CONFIG_ARCH_TEGRA_2x_SOC)
  322. writel_relaxed(0x331, p + L2X0_TAG_LATENCY_CTRL);
  323. writel_relaxed(0x441, p + L2X0_DATA_LATENCY_CTRL);
  324.  
  325. #elif defined(CONFIG_ARCH_TEGRA_3x_SOC)
  326. #ifdef CONFIG_TEGRA_SILICON_PLATFORM
  327. /* PL310 RAM latency is CPU dependent. NOTE: Changes here
  328. must also be reflected in __cortex_a9_l2x0_restart */
  329.  
  330. if (is_lp_cluster()) {
  331. writel(0x221, p + L2X0_TAG_LATENCY_CTRL);
  332. writel(0x221, p + L2X0_DATA_LATENCY_CTRL);
  333. } else {
  334. u32 speedo;
  335.  
  336. /* relax l2-cache latency for speedos 4,5,6 (T33's chips) */
  337. speedo = tegra_cpu_speedo_id();
  338. if (speedo == 4 || speedo == 5 || speedo == 6 ||
  339. speedo == 12 || speedo == 13) {
  340. writel(0x442, p + L2X0_TAG_LATENCY_CTRL);
  341. writel(0x552, p + L2X0_DATA_LATENCY_CTRL);
  342. } else {
  343. writel(0x441, p + L2X0_TAG_LATENCY_CTRL);
  344. writel(0x551, p + L2X0_DATA_LATENCY_CTRL);
  345. }
  346. }
  347. #else
  348. writel(0x770, p + L2X0_TAG_LATENCY_CTRL);
  349. writel(0x770, p + L2X0_DATA_LATENCY_CTRL);
  350. #endif
  351. #endif
  352. writel(0x3, p + L2X0_POWER_CTRL);
  353. aux_ctrl = readl(p + L2X0_CACHE_TYPE);
  354. aux_ctrl = (aux_ctrl & 0x700) << (17-8);
  355. aux_ctrl |= 0x7C000001;
  356. if (init) {
  357. l2x0_init(p, aux_ctrl, 0x8200c3fe);
  358. } else {
  359. u32 tmp;
  360.  
  361. tmp = aux_ctrl;
  362. aux_ctrl = readl(p + L2X0_AUX_CTRL);
  363. aux_ctrl &= 0x8200c3fe;
  364. aux_ctrl |= tmp;
  365. writel(aux_ctrl, p + L2X0_AUX_CTRL);
  366. }
  367. l2x0_enable();
  368. #endif
  369. }
  370. #endif
  371.  
  372. static void __init tegra_init_power(void)
  373. {
  374. #ifdef CONFIG_ARCH_TEGRA_HAS_SATA
  375. tegra_powergate_partition_with_clk_off(TEGRA_POWERGATE_SATA);
  376. #endif
  377. #ifdef CONFIG_ARCH_TEGRA_HAS_PCIE
  378. tegra_powergate_partition_with_clk_off(TEGRA_POWERGATE_PCIE);
  379. #endif
  380. }
  381.  
  382. static inline unsigned long gizmo_readl(unsigned long offset)
  383. {
  384. return readl(IO_TO_VIRT(TEGRA_AHB_GIZMO_BASE + offset));
  385. }
  386.  
  387. static inline void gizmo_writel(unsigned long value, unsigned long offset)
  388. {
  389. writel(value, IO_TO_VIRT(TEGRA_AHB_GIZMO_BASE + offset));
  390. }
  391.  
  392. static void __init tegra_init_ahb_gizmo_settings(void)
  393. {
  394. unsigned long val;
  395.  
  396. val = gizmo_readl(AHB_GIZMO_AHB_MEM);
  397. val |= ENB_FAST_REARBITRATE | IMMEDIATE | DONT_SPLIT_AHB_WR;
  398. gizmo_writel(val, AHB_GIZMO_AHB_MEM);
  399.  
  400. val = gizmo_readl(AHB_GIZMO_USB);
  401. val |= IMMEDIATE;
  402. gizmo_writel(val, AHB_GIZMO_USB);
  403.  
  404. val = gizmo_readl(AHB_GIZMO_USB2);
  405. val |= IMMEDIATE;
  406. gizmo_writel(val, AHB_GIZMO_USB2);
  407.  
  408. val = gizmo_readl(AHB_GIZMO_USB3);
  409. val |= IMMEDIATE;
  410. gizmo_writel(val, AHB_GIZMO_USB3);
  411.  
  412. val = gizmo_readl(AHB_ARBITRATION_PRIORITY_CTRL);
  413. val |= PRIORITY_SELECT_USB | PRIORITY_SELECT_USB2 | PRIORITY_SELECT_USB3
  414. | AHB_PRIORITY_WEIGHT(7);
  415. gizmo_writel(val, AHB_ARBITRATION_PRIORITY_CTRL);
  416.  
  417. val = gizmo_readl(AHB_MEM_PREFETCH_CFG1);
  418. val &= ~MST_ID(~0);
  419. val |= PREFETCH_ENB | AHBDMA_MST_ID | ADDR_BNDRY(0xc) | INACTIVITY_TIMEOUT(0x1000);
  420. gizmo_writel(val, AHB_MEM_PREFETCH_CFG1);
  421.  
  422. val = gizmo_readl(AHB_MEM_PREFETCH_CFG2);
  423. val &= ~MST_ID(~0);
  424. val |= PREFETCH_ENB | USB_MST_ID | ADDR_BNDRY(0xc) | INACTIVITY_TIMEOUT(0x1000);
  425. gizmo_writel(val, AHB_MEM_PREFETCH_CFG2);
  426.  
  427. val = gizmo_readl(AHB_MEM_PREFETCH_CFG3);
  428. val &= ~MST_ID(~0);
  429. val |= PREFETCH_ENB | USB3_MST_ID | ADDR_BNDRY(0xc) | INACTIVITY_TIMEOUT(0x1000);
  430. gizmo_writel(val, AHB_MEM_PREFETCH_CFG3);
  431.  
  432. val = gizmo_readl(AHB_MEM_PREFETCH_CFG4);
  433. val &= ~MST_ID(~0);
  434. val |= PREFETCH_ENB | USB2_MST_ID | ADDR_BNDRY(0xc) | INACTIVITY_TIMEOUT(0x1000);
  435. gizmo_writel(val, AHB_MEM_PREFETCH_CFG4);
  436. }
  437.  
  438. void __init tegra_init_early(void)
  439. {
  440. #ifndef CONFIG_SMP
  441. /* For SMP system, initializing the reset handler here is too
  442. late. For non-SMP systems, the function that calls the reset
  443. handler initializer is not called, so do it here for non-SMP. */
  444. tegra_cpu_reset_handler_init();
  445. #endif
  446. tegra_init_fuse();
  447. tegra_gpio_resume_init();
  448. tegra_init_clock();
  449. tegra_init_pinmux();
  450. tegra_clk_init_from_table(common_clk_init_table);
  451. tegra_init_power();
  452. tegra_init_cache(true);
  453. tegra_init_ahb_gizmo_settings();
  454. tegra_init_debug_uart_rate();
  455. }
  456.  
  457. static int __init tegra_lp0_vec_arg(char *options)
  458. {
  459. char *p = options;
  460.  
  461. tegra_lp0_vec_size = memparse(p, &p);
  462. if (*p == '@')
  463. tegra_lp0_vec_start = memparse(p+1, &p);
  464. if (!tegra_lp0_vec_size || !tegra_lp0_vec_start) {
  465. tegra_lp0_vec_size = 0;
  466. tegra_lp0_vec_start = 0;
  467. }
  468.  
  469. return 0;
  470. }
  471. early_param("lp0_vec", tegra_lp0_vec_arg);
  472.  
  473. static int __init tegra_bootloader_fb_arg(char *options)
  474. {
  475. char *p = options;
  476.  
  477. tegra_bootloader_fb_size = memparse(p, &p);
  478. if (*p == '@')
  479. tegra_bootloader_fb_start = memparse(p+1, &p);
  480.  
  481. pr_info("Found tegra_fbmem: %08lx@%08lx\n",
  482. tegra_bootloader_fb_size, tegra_bootloader_fb_start);
  483.  
  484. return 0;
  485. }
  486. early_param("tegra_fbmem", tegra_bootloader_fb_arg);
  487.  
  488. static int __init tegra_sku_override(char *id)
  489. {
  490. char *p = id;
  491.  
  492. sku_override = memparse(p, &p);
  493.  
  494. return 0;
  495. }
  496. early_param("sku_override", tegra_sku_override);
  497.  
  498. int tegra_get_sku_override(void)
  499. {
  500. return sku_override;
  501. }
  502.  
  503. static int __init tegra_vpr_arg(char *options)
  504. {
  505. char *p = options;
  506.  
  507. tegra_vpr_size = memparse(p, &p);
  508. if (*p == '@')
  509. tegra_vpr_start = memparse(p+1, &p);
  510. pr_info("Found vpr, start=0x%lx size=%lx",
  511. tegra_vpr_start, tegra_vpr_size);
  512. return 0;
  513. }
  514. early_param("vpr", tegra_vpr_arg);
  515.  
  516. enum panel_type get_panel_type(void)
  517. {
  518. return board_panel_type;
  519. }
  520. static int __init tegra_board_panel_type(char *options)
  521. {
  522. if (!strcmp(options, "lvds"))
  523. board_panel_type = panel_type_lvds;
  524. else if (!strcmp(options, "dsi"))
  525. board_panel_type = panel_type_dsi;
  526. else
  527. return 0;
  528. return 1;
  529. }
  530. __setup("panel=", tegra_board_panel_type);
  531.  
  532. enum power_supply_type get_power_supply_type(void)
  533. {
  534. return pow_supply_type;
  535. }
  536. static int __init tegra_board_power_supply_type(char *options)
  537. {
  538. if (!strcmp(options, "Adapter"))
  539. pow_supply_type = POWER_SUPPLY_TYPE_MAINS;
  540. if (!strcmp(options, "Mains"))
  541. pow_supply_type = POWER_SUPPLY_TYPE_MAINS;
  542. else if (!strcmp(options, "Battery"))
  543. pow_supply_type = POWER_SUPPLY_TYPE_BATTERY;
  544. else
  545. return 0;
  546. return 1;
  547. }
  548. __setup("power_supply=", tegra_board_power_supply_type);
  549.  
  550. int get_core_edp(void)
  551. {
  552. return pmu_core_edp;
  553. }
  554. static int __init tegra_pmu_core_edp(char *options)
  555. {
  556. char *p = options;
  557. int core_edp = memparse(p, &p);
  558. if (core_edp != 0)
  559. pmu_core_edp = core_edp;
  560. return 0;
  561. }
  562. early_param("core_edp_mv", tegra_pmu_core_edp);
  563.  
  564. int get_maximum_cpu_current_supported(void)
  565. {
  566. return max_cpu_current;
  567. }
  568. static int __init tegra_max_cpu_current(char *options)
  569. {
  570. char *p = options;
  571. max_cpu_current = memparse(p, &p);
  572. return 1;
  573. }
  574. __setup("max_cpu_cur_ma=", tegra_max_cpu_current);
  575.  
  576. static int __init tegra_debug_uartport(char *info)
  577. {
  578. char *p = info;
  579. unsigned long long port_id;
  580. if (!strncmp(p, "hsport", 6))
  581. is_tegra_debug_uart_hsport = true;
  582. else if (!strncmp(p, "lsport", 6))
  583. is_tegra_debug_uart_hsport = false;
  584.  
  585. if (p[6] == ',') {
  586. if (p[7] == '-') {
  587. debug_uart_port_id = -1;
  588. } else {
  589. port_id = memparse(p + 7, &p);
  590. debug_uart_port_id = (int) port_id;
  591. }
  592. } else {
  593. debug_uart_port_id = -1;
  594. }
  595.  
  596. return 1;
  597. }
  598.  
  599. bool is_tegra_debug_uartport_hs(void)
  600. {
  601. return is_tegra_debug_uart_hsport;
  602. }
  603.  
  604. int get_tegra_uart_debug_port_id(void)
  605. {
  606. return debug_uart_port_id;
  607. }
  608. __setup("debug_uartport=", tegra_debug_uartport);
  609.  
  610. static int __init tegra_image_type(char *options)
  611. {
  612. if (!strcmp(options, "RCK"))
  613. board_image_type = rck_image;
  614.  
  615. return 0;
  616. }
  617.  
  618. enum image_type get_tegra_image_type(void)
  619. {
  620. return board_image_type;
  621. }
  622.  
  623. __setup("image=", tegra_image_type);
  624.  
  625. static int __init tegra_audio_codec_type(char *info)
  626. {
  627. char *p = info;
  628. if (!strncmp(p, "wm8903", 6))
  629. audio_codec_name = audio_codec_wm8903;
  630. else
  631. audio_codec_name = audio_codec_none;
  632.  
  633. return 1;
  634. }
  635.  
  636. enum audio_codec_type get_audio_codec_type(void)
  637. {
  638. return audio_codec_name;
  639. }
  640. __setup("audio_codec=", tegra_audio_codec_type);
  641.  
  642.  
  643. void tegra_get_board_info(struct board_info *bi)
  644. {
  645. bi->board_id = (system_serial_high >> 16) & 0xFFFF;
  646. bi->sku = (system_serial_high) & 0xFFFF;
  647. bi->fab = (system_serial_low >> 24) & 0xFF;
  648. bi->major_revision = (system_serial_low >> 16) & 0xFF;
  649. bi->minor_revision = (system_serial_low >> 8) & 0xFF;
  650. }
  651.  
  652. static int __init tegra_pmu_board_info(char *info)
  653. {
  654. char *p = info;
  655. pmu_board_info.board_id = memparse(p, &p);
  656. pmu_board_info.sku = memparse(p+1, &p);
  657. pmu_board_info.fab = memparse(p+1, &p);
  658. pmu_board_info.major_revision = memparse(p+1, &p);
  659. pmu_board_info.minor_revision = memparse(p+1, &p);
  660. return 1;
  661. }
  662.  
  663. void tegra_get_pmu_board_info(struct board_info *bi)
  664. {
  665. memcpy(bi, &pmu_board_info, sizeof(struct board_info));
  666. }
  667.  
  668. __setup("pmuboard=", tegra_pmu_board_info);
  669.  
  670. static int __init tegra_display_board_info(char *info)
  671. {
  672. char *p = info;
  673. display_board_info.board_id = memparse(p, &p);
  674. display_board_info.sku = memparse(p+1, &p);
  675. display_board_info.fab = memparse(p+1, &p);
  676. display_board_info.major_revision = memparse(p+1, &p);
  677. display_board_info.minor_revision = memparse(p+1, &p);
  678. return 1;
  679. }
  680.  
  681. void tegra_get_display_board_info(struct board_info *bi)
  682. {
  683. memcpy(bi, &display_board_info, sizeof(struct board_info));
  684. }
  685.  
  686. __setup("displayboard=", tegra_display_board_info);
  687.  
  688. static int __init tegra_camera_board_info(char *info)
  689. {
  690. char *p = info;
  691. camera_board_info.board_id = memparse(p, &p);
  692. camera_board_info.sku = memparse(p+1, &p);
  693. camera_board_info.fab = memparse(p+1, &p);
  694. camera_board_info.major_revision = memparse(p+1, &p);
  695. camera_board_info.minor_revision = memparse(p+1, &p);
  696. return 1;
  697. }
  698.  
  699. void tegra_get_camera_board_info(struct board_info *bi)
  700. {
  701. memcpy(bi, &camera_board_info, sizeof(struct board_info));
  702. }
  703.  
  704. __setup("cameraboard=", tegra_camera_board_info);
  705.  
  706. static int __init tegra_modem_id(char *id)
  707. {
  708. char *p = id;
  709.  
  710. modem_id = memparse(p, &p);
  711. return 1;
  712. }
  713.  
  714. int tegra_get_modem_id(void)
  715. {
  716. return modem_id;
  717. }
  718.  
  719. __setup("modem_id=", tegra_modem_id);
  720.  
  721. static int __init tegra_commchip_id(char *id)
  722. {
  723. char *p = id;
  724.  
  725. if (get_option(&p, &commchip_id) != 1)
  726. return 0;
  727. return 1;
  728. }
  729.  
  730. int tegra_get_commchip_id(void)
  731. {
  732. return commchip_id;
  733. }
  734.  
  735. __setup("commchip_id=", tegra_commchip_id);
  736.  
  737. /*
  738. * Tegra has a protected aperture that prevents access by most non-CPU
  739. * memory masters to addresses above the aperture value. Enabling it
  740. * secures the CPU's memory from the GPU, except through the GART.
  741. */
  742. void __init tegra_protected_aperture_init(unsigned long aperture)
  743. {
  744. #ifndef CONFIG_NVMAP_ALLOW_SYSMEM
  745. void __iomem *mc_base = IO_ADDRESS(TEGRA_MC_BASE);
  746. pr_info("Enabling Tegra protected aperture at 0x%08lx\n", aperture);
  747. writel(aperture, mc_base + MC_SECURITY_CFG2);
  748. #else
  749. pr_err("Tegra protected aperture disabled because nvmap is using "
  750. "system memory\n");
  751. #endif
  752. }
  753.  
  754. /*
  755. * Due to conflicting restrictions on the placement of the framebuffer,
  756. * the bootloader is likely to leave the framebuffer pointed at a location
  757. * in memory that is outside the grhost aperture. This function will move
  758. * the framebuffer contents from a physical address that is anywher (lowmem,
  759. * highmem, or outside the memory map) to a physical address that is outside
  760. * the memory map.
  761. */
  762.  
  763.  
  764. unsigned int to_rgb888(unsigned int temp)
  765. {
  766. unsigned int red, green, blue;
  767. red = (temp >> 11) & 0x1F;
  768. green = (temp >> 5) & 0x3F;
  769. blue = (temp & 0x001F);
  770. red = (red << 3) | (red >> 2);
  771. green = (green << 2) | (green >> 4);
  772. blue = (blue << 3) | (blue >> 2);
  773. return (blue << 16) | (green << 8) | (red << 0);
  774. }
  775.  
  776. void tegra_move_framebuffer(unsigned long to, unsigned long from,
  777. unsigned long to_size, unsigned long from_size)
  778. {
  779. struct page *page;
  780. void __iomem *to_io;
  781. u16 *from_virt;
  782. unsigned long i, j;
  783.  
  784. BUG_ON(PAGE_ALIGN((unsigned long)to) != (unsigned long)to);
  785. BUG_ON(PAGE_ALIGN(from) != from);
  786. BUG_ON(PAGE_ALIGN(to_size) != to_size);
  787. BUG_ON(PAGE_ALIGN(from_size) != from_size);
  788.  
  789. to_io = ioremap(to, to_size);
  790. if (!to_io) {
  791. pr_err("%s: Failed to map target framebuffer\n", __func__);
  792. return;
  793. }
  794.  
  795. if (pfn_valid(page_to_pfn(phys_to_page(from)))) {
  796. for (i = 0 ; i < from_size; i += PAGE_SIZE) {
  797. page = phys_to_page(from + i);
  798. from_virt = kmap(page);
  799.  
  800. for (j = 0; j < PAGE_SIZE; j += 2)
  801. writel(to_rgb888(*(from_virt+j)), to_io + 2*j + i);
  802.  
  803. kunmap(page);
  804. }
  805. } else {
  806. void __iomem *from_io = ioremap(from, from_size);
  807. if (!from_io) {
  808. pr_err("%s: Failed to map source framebuffer\n",
  809. __func__);
  810. goto out;
  811. }
  812.  
  813. for (i = 0; i < from_size; i += 2)
  814. writel(to_rgb888(readw(from_io + i)), to_io + 2*i);
  815.  
  816. iounmap(from_io);
  817. }
  818. out:
  819. iounmap(to_io);
  820. }
  821.  
  822.  
  823. void __init tegra_reserve(unsigned long carveout_size, unsigned long fb_size,
  824. unsigned long fb2_size)
  825. {
  826. if (carveout_size) {
  827. tegra_carveout_start = memblock_end_of_DRAM() - carveout_size;
  828. if (memblock_remove(tegra_carveout_start, carveout_size)) {
  829. pr_err("Failed to remove carveout %08lx@%08lx "
  830. "from memory map\n",
  831. carveout_size, tegra_carveout_start);
  832. tegra_carveout_start = 0;
  833. tegra_carveout_size = 0;
  834. } else
  835. tegra_carveout_size = carveout_size;
  836. }
  837.  
  838. if (fb2_size) {
  839. tegra_fb2_start = memblock_end_of_DRAM() - fb2_size;
  840. if (memblock_remove(tegra_fb2_start, fb2_size)) {
  841. pr_err("Failed to remove second framebuffer "
  842. "%08lx@%08lx from memory map\n",
  843. fb2_size, tegra_fb2_start);
  844. tegra_fb2_start = 0;
  845. tegra_fb2_size = 0;
  846. } else
  847. tegra_fb2_size = fb2_size;
  848. }
  849.  
  850. if (fb_size) {
  851. tegra_fb_start = memblock_end_of_DRAM() - fb_size;
  852. if (memblock_remove(tegra_fb_start, fb_size)) {
  853. pr_err("Failed to remove framebuffer %08lx@%08lx "
  854. "from memory map\n",
  855. fb_size, tegra_fb_start);
  856. tegra_fb_start = 0;
  857. tegra_fb_size = 0;
  858. } else
  859. tegra_fb_size = fb_size;
  860. }
  861.  
  862. if (tegra_fb_size)
  863. tegra_grhost_aperture = tegra_fb_start;
  864.  
  865. if (tegra_fb2_size && tegra_fb2_start < tegra_grhost_aperture)
  866. tegra_grhost_aperture = tegra_fb2_start;
  867.  
  868. if (tegra_carveout_size && tegra_carveout_start < tegra_grhost_aperture)
  869. tegra_grhost_aperture = tegra_carveout_start;
  870.  
  871. if (tegra_lp0_vec_size &&
  872. (tegra_lp0_vec_start < memblock_end_of_DRAM())) {
  873. if (memblock_reserve(tegra_lp0_vec_start, tegra_lp0_vec_size)) {
  874. pr_err("Failed to reserve lp0_vec %08lx@%08lx\n",
  875. tegra_lp0_vec_size, tegra_lp0_vec_start);
  876. tegra_lp0_vec_start = 0;
  877. tegra_lp0_vec_size = 0;
  878. }
  879. tegra_lp0_vec_relocate = false;
  880. } else
  881. tegra_lp0_vec_relocate = true;
  882.  
  883. /*
  884. * We copy the bootloader's framebuffer to the framebuffer allocated
  885. * above, and then free this one.
  886. * */
  887. if (tegra_bootloader_fb_size) {
  888. tegra_bootloader_fb_size = PAGE_ALIGN(tegra_bootloader_fb_size);
  889. if (memblock_reserve(tegra_bootloader_fb_start,
  890. tegra_bootloader_fb_size)) {
  891. pr_err("Failed to reserve bootloader frame buffer "
  892. "%08lx@%08lx\n", tegra_bootloader_fb_size,
  893. tegra_bootloader_fb_start);
  894. tegra_bootloader_fb_start = 0;
  895. tegra_bootloader_fb_size = 0;
  896. }
  897. }
  898.  
  899. pr_info("Tegra reserved memory:\n"
  900. "LP0: %08lx - %08lx\n"
  901. "Bootloader framebuffer: %08lx - %08lx\n"
  902. "Framebuffer: %08lx - %08lx\n"
  903. "2nd Framebuffer: %08lx - %08lx\n"
  904. "Carveout: %08lx - %08lx\n"
  905. "Vpr: %08lx - %08lx\n",
  906. tegra_lp0_vec_start,
  907. tegra_lp0_vec_size ?
  908. tegra_lp0_vec_start + tegra_lp0_vec_size - 1 : 0,
  909. tegra_bootloader_fb_start,
  910. tegra_bootloader_fb_size ?
  911. tegra_bootloader_fb_start + tegra_bootloader_fb_size - 1 : 0,
  912. tegra_fb_start,
  913. tegra_fb_size ?
  914. tegra_fb_start + tegra_fb_size - 1 : 0,
  915. tegra_fb2_start,
  916. tegra_fb2_size ?
  917. tegra_fb2_start + tegra_fb2_size - 1 : 0,
  918. tegra_carveout_start,
  919. tegra_carveout_size ?
  920. tegra_carveout_start + tegra_carveout_size - 1 : 0,
  921. tegra_vpr_start,
  922. tegra_vpr_size ?
  923. tegra_vpr_start + tegra_vpr_size - 1 : 0);
  924. }
  925.  
  926. static struct resource ram_console_resources[] = {
  927. {
  928. .flags = IORESOURCE_MEM,
  929. },
  930. };
  931.  
  932. static struct platform_device ram_console_device = {
  933. .name = "ram_console",
  934. .id = -1,
  935. .num_resources = ARRAY_SIZE(ram_console_resources),
  936. .resource = ram_console_resources,
  937. };
  938.  
  939. void __init tegra_ram_console_debug_reserve(unsigned long ram_console_size)
  940. {
  941. struct resource *res;
  942. long ret;
  943.  
  944. res = platform_get_resource(&ram_console_device, IORESOURCE_MEM, 0);
  945. if (!res)
  946. goto fail;
  947. res->start = memblock_end_of_DRAM() - ram_console_size;
  948. res->end = res->start + ram_console_size - 1;
  949. ret = memblock_remove(res->start, ram_console_size);
  950. if (ret)
  951. goto fail;
  952.  
  953. return;
  954.  
  955. fail:
  956. ram_console_device.resource = NULL;
  957. ram_console_device.num_resources = 0;
  958. pr_err("Failed to reserve memory block for ram console\n");
  959. }
  960.  
  961. void __init tegra_ram_console_debug_init(void)
  962. {
  963. int err;
  964.  
  965. err = platform_device_register(&ram_console_device);
  966. if (err) {
  967. pr_err("%s: ram console registration failed (%d)!\n", __func__, err);
  968. }
  969. }
  970.  
  971. void __init tegra_release_bootloader_fb(void)
  972. {
  973. /* Since bootloader fb is reserved in common.c, it is freed here. */
  974. if (tegra_bootloader_fb_size)
  975. if (memblock_free(tegra_bootloader_fb_start,
  976. tegra_bootloader_fb_size))
  977. pr_err("Failed to free bootloader fb.\n");
  978. }
  979.  
  980. #ifdef CONFIG_TEGRA_CONVSERVATIVE_GOV_ON_EARLYSUPSEND
  981. char cpufreq_default_gov[CONFIG_NR_CPUS][MAX_GOV_NAME_LEN];
  982. char *cpufreq_conservative_gov = "conservative";
  983.  
  984. void cpufreq_store_default_gov(void)
  985. {
  986. unsigned int cpu;
  987. struct cpufreq_policy *policy;
  988.  
  989. for (cpu = 0; cpu < CONFIG_NR_CPUS; cpu++) {
  990. policy = cpufreq_cpu_get(cpu);
  991. if (policy) {
  992. sprintf(cpufreq_default_gov[cpu], "%s",
  993. policy->governor->name);
  994. cpufreq_cpu_put(policy);
  995. }
  996. }
  997. }
  998.  
  999. int cpufreq_change_gov(char *target_gov)
  1000. {
  1001. unsigned int cpu = 0;
  1002.  
  1003. #ifndef CONFIG_TEGRA_AUTO_HOTPLUG
  1004. for_each_online_cpu(cpu)
  1005. #endif
  1006. return cpufreq_set_gov(target_gov, cpu);
  1007. }
  1008.  
  1009. int cpufreq_restore_default_gov(void)
  1010. {
  1011. int ret = 0;
  1012. unsigned int cpu;
  1013.  
  1014. for (cpu = 0; cpu < CONFIG_NR_CPUS; cpu++) {
  1015. if (strlen((const char *)&cpufreq_default_gov[cpu])) {
  1016. ret = cpufreq_set_gov(cpufreq_default_gov[cpu], cpu);
  1017. if (ret < 0)
  1018. /* Unable to restore gov for the cpu as
  1019. * It was online on suspend and becomes
  1020. * offline on resume.
  1021. */
  1022. pr_info("Unable to restore gov:%s for cpu:%d,"
  1023. , cpufreq_default_gov[cpu]
  1024. , cpu);
  1025. }
  1026. cpufreq_default_gov[cpu][0] = '\0';
  1027. }
  1028. return ret;
  1029. }
  1030. #endif /* CONFIG_TEGRA_CONVSERVATIVE_GOV_ON_EARLYSUPSEND */
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