misoc efc patch

diff --git a/misoc/targets/efc.py b/misoc/targets/efc.py
index abf4872d..11609737 100644
--- a/misoc/targets/efc.py
+++ b/misoc/targets/efc.py
@@ -35,22 +35,23 @@ class AsyncResetSynchronizerBUFG(Module):


 class _RtioSysCRG(Module, AutoCSR):
-    def __init__(self, platform):
+    def __init__(self, platform, sys_freq=125e6):
         self.clock_domains.cd_sys = ClockDomain()
         self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
         self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True)
         self.clock_domains.cd_sys5x = ClockDomain(reset_less=True)
         self.clock_domains.cd_clk200 = ClockDomain()

-        clk125 = platform.request("gtp_clk")
-        platform.add_period_constraint(clk125, 8.)
-        self.clk125_buf = Signal()
-        self.clk125_div2 = Signal()
+        gtp_clk = platform.request("gtp_clk")
+        gtp_clk_period = 1e9/sys_freq
+        platform.add_period_constraint(gtp_clk, gtp_clk_period)
+        self.gtp_clk_buf = Signal()
+        self.gtp_clk_div2 = Signal()
         self.specials += Instance("IBUFDS_GTE2",
             i_CEB=0,
-            i_I=clk125.p, i_IB=clk125.n,
-            o_O=self.clk125_buf,
-            o_ODIV2=self.clk125_div2,
+            i_I=gtp_clk.p, i_IB=gtp_clk.n,
+            o_O=self.gtp_clk_buf,
+            o_ODIV2=self.gtp_clk_div2,
             p_CLKCM_CFG="TRUE",
             p_CLKRCV_TRST="TRUE",
             p_CLKSWING_CFG=3)
@@ -58,10 +59,12 @@ class _RtioSysCRG(Module, AutoCSR):
         pll_clk200 = Signal()
         pll_fb = Signal()
         self.pll_locked = Signal()
+
+        clk_200_div_ratio = round(sys_freq/2.0*16/200e6)
         self.specials += [
             Instance("PLLE2_BASE",
-                p_CLKIN1_PERIOD=16.0,
-                i_CLKIN1=self.clk125_div2,
+                p_CLKIN1_PERIOD=gtp_clk_period*2.,
+                i_CLKIN1=self.gtp_clk_div2,

                 i_CLKFBIN=pll_fb,
                 o_CLKFBOUT=pll_fb,
@@ -74,7 +77,7 @@ class _RtioSysCRG(Module, AutoCSR):
                 # The OOB reset mechanism only resets the MMCM that generates the sysclk,
                 # clk200 is generated by a PLL parallel to that MMCM, hence not affected
                 # by the reset.
-                p_CLKOUT0_DIVIDE=5, p_CLKOUT0_PHASE=0.0, o_CLKOUT0=pll_clk200,
+                p_CLKOUT0_DIVIDE=clk_200_div_ratio, p_CLKOUT0_PHASE=0.0, o_CLKOUT0=pll_clk200,
             ),
             Instance("BUFG", i_I=pll_clk200, o_O=self.cd_clk200.clk),
             AsyncResetSynchronizer(self.cd_clk200, ~self.pll_locked),
@@ -102,8 +105,8 @@ class _RtioSysCRG(Module, AutoCSR):
         self.reset = Signal()
         self.specials += [
             Instance("MMCME2_BASE",
-                p_CLKIN1_PERIOD=16.0,
-                i_CLKIN1=self.clk125_div2,
+                p_CLKIN1_PERIOD=gtp_clk_period*2.,
+                i_CLKIN1=self.gtp_clk_div2,

                 i_RST=self.reset,

@@ -129,7 +132,7 @@ class _RtioSysCRG(Module, AutoCSR):
             Instance("BUFG", i_I=mmcm_fb_out, o_O=mmcm_fb_in),

             Instance("MMCME2_BASE",
-                p_CLKIN1_PERIOD=2.0,
+                p_CLKIN1_PERIOD=gtp_clk_period/4.,
                 i_CLKIN1=self.cd_sys4x.clk,

                 i_RST=~mmcm_locked,
@@ -161,7 +164,7 @@ class BaseSoC(SoCSDRAM):

         self.config["HW_REV"] = hw_rev

-        self.submodules.crg = _RtioSysCRG(platform)
+        self.submodules.crg = _RtioSysCRG(platform, clk_freq)
         self.csr_devices.append("crg")

         self.platform.add_period_constraint(self.crg.cd_sys.clk, 1e9/self.clk_freq)