module spram
  #(
    parameter ADDR_WIDTH = 32
    )
   (
    input 		   clk,
    input [ADDR_WIDTH-1:0] addr,
    input 		   we,
    input [3:0] 	   bsel,
    input [31:0] 	   din,
    output reg [31:0] 	   dout
    );

   reg [7:0] 		    mem0[(1<<ADDR_WIDTH)-1:0];
   reg [7:0] 		    mem1[(1<<ADDR_WIDTH)-1:0];
   reg [7:0] 		    mem2[(1<<ADDR_WIDTH)-1:0];
   reg [7:0] 		    mem3[(1<<ADDR_WIDTH)-1:0];

   always @(posedge clk) begin
      if (we) begin
	 if (bsel[3])
	   mem3[addr] <= din[31:24];
	 if (bsel[2])
	   mem2[addr] <= din[23:16];
	 if (bsel[1])
	   mem1[addr] <= din[15:8];
	 if (bsel[0])
	   mem0[addr] <= din[7:0];
      end
      dout <= {mem3[addr], mem2[addr], mem1[addr], mem0[addr]};
   end

endmodule