class TestFSM(Module):
    def __init__(self):
        self.a = Signal()
        self.b = Signal()
        self.n = Signal()
        fsm = FSM(reset_state="STATE0")
        self.submodules += fsm

        fsm.act("STATE0",
               self.a.eq(self.b),
               If(self.n, NextState("STATE1")))

        fsm.act("STATE1",
               If(~self.n, NextState("STATE0")))

dut = TestFSM()
print(verilog.convert(dut))


"""
--> OUTPUTS
/* Machine-generated using Migen */
module top(
    input sys_clk,
    input sys_rst
);

reg a = 1'd0;
reg b = 1'd0;
reg n = 1'd0;
reg state = 1'd0;
reg next_state = 1'd0;

// synthesis translate_off
reg dummy_s;
initial dummy_s <= 1'd0;
// synthesis translate_on

// synthesis translate_off
reg dummy_d;
// synthesis translate_on
always @(*) begin
    a <= 1'd0;
    next_state <= 1'd0;
    next_state <= state;
    case (state)
        1'd1: begin
            if ((~n)) begin
                next_state <= 1'd0;
            end
        end
        default: begin
            a <= b;
            if (n) begin
                next_state <= 1'd1;
            end
        end
    endcase
// synthesis translate_off
    dummy_d <= dummy_s;
// synthesis translate_on
end

always @(posedge sys_clk) begin
    if (sys_rst) begin
        state <= 1'd0;
    end else begin
        state <= next_state;
    end
end

endmodule
"""