tak

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY hex7seg IS
	PORT (	hex		: integer range 0 to 15;
				display	: OUT	STD_LOGIC_VECTOR(0 TO 6));
END hex7seg;

ARCHITECTURE Behavior OF hex7seg IS
BEGIN
	--
	--       0
	--      ---
	--     |   |
	--    5|   |1
	--     | 6 |
	--      ---
	--     |   |
	--    4|   |2
	--     |   |
	--      ---
	--       3
	--
	PROCESS (hex)
	BEGIN
		CASE hex IS
			WHEN 0 => display <= "0000001";
			WHEN 1 => display <= "1001111";
			WHEN 2 => display <= "0010010";
			WHEN 3 => display <= "0000110";
			WHEN 4 => display <= "1001100";
			WHEN 5 => display <= "0100100";
			WHEN 6 => display <= "1100000";
			WHEN 7 => display <= "0001111";
			WHEN 8 => display <= "0000000";
			WHEN 9 => display <= "0001100";
			WHEN 10 => display <= "0001000";
			WHEN 11 => display <= "1100000";
			WHEN 12 => display <= "0110001";
			WHEN 13 => display <= "1000010";
			WHEN 14 => display <= "0110000";
			WHEN OTHERS => display <= "0111000";
		END CASE;
	END PROCESS;
END Behavior;




















LIBRARY ieee;
USE ieee.std_logic_1164.all;


entity licznik is
	port(
	CLK : in std_logic;
	HEX0 : out std_logic_vector (0 to 6));
end licznik;

architecture beh of licznik is

component hex7seg is
	port( hex : integer range 0 to 15;
	display : OUT std_logic_vector( 0 to 6 ));
	end component;

	constant countlimit : integer := 500000000;
	signal currentCount : integer range 0 to 214748364 :=0;
	signal digit : integer range 0 to 15 :=0;
	signal HEXTMP : std_logic_vector (0 to 6);

	begin

	SEG0 : hex7seg port map(hex=>digit, display=>HEXTMP);

	process1 : process(CLK)
		begin
		if(CLK'event and CLK = '1')
		then currentCount <= currentCount +1;
		end if;

		if(CurrentCount >= countLimit) then
		digit <= digit +1;
		CurrentCount <= 0;
		end if;

		end process;

		process2: process(digit)
			begin
			HEX0 <= HEXTMP;
			end process;

end beh;