How to design a simple Adder with separate carry and borrow flags?
entity carryover is
  port(
    DataIn: in std_logic_vector(7 downto 0);
    SegmentIn: in std_logic_vector(7 downto 0);
    Addend: in std_logic_vector(7 downto 0); --How much to increase DataIn by (as a signed number). Believe it or not, that's the actual word for what we need.
    DataOut: out std_logic_vector(7 downto 0);
    SegmentOut: out std_logic_vector(7 downto 0);
   );
end carryover;

architecture Behavioral of carryover is
  signal temp: std_logic_vector(8 downto 0);
begin
  --treat as unsigned because it doesn't actually matter for addition and just make carry and borrow correct
  temp <= std_logic_vector(unsigned("0" & DataIn) + (unsigned)Addend);
  DataOut <= temp(7 downto 0);
  SegmentOut <= unsigned(SegmentIn) + 1 when (not temp(8)) and (not Addend(7)

end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.tinycpu.all;

entity carryover is
  port(
    EnableCarry: in std_logic; --When disabled, SegmentIn goes to SegmentOut
    DataIn: in std_logic_vector(7 downto 0);
    SegmentIn: in std_logic_vector(7 downto 0);
    Addend: in std_logic_vector(7 downto 0); --How much to increase DataIn by (as a signed number). Believe it or not, that's the actual word for what we need.
    DataOut: out std_logic_vector(7 downto 0);
    SegmentOut: out std_logic_vector(7 downto 0)
--    Debug: out std_logic_vector(8 downto 0)
   );
end carryover;

architecture Behavioral of carryover is
  signal temp: std_logic_vector(8 downto 0);
begin
  --treat as unsigned because it doesn't actually matter for addition and just make carry and borrow correct
  process(DataIn, SegmentIn,Addend, EnableCarry)
  begin
    temp <= std_logic_vector(signed('0' & DataIn) + signed(Addend(7) & Addend));
    if (EnableCarry and ((not Addend(7)) and (DataIn(7)) and temp(8)))='1' then
      SegmentOut <= std_logic_vector(unsigned(SegmentIn)+1);
    elsif (EnableCarry and (Addend(7) and (not DataIn(7)) and temp(8)))='1' then
      SegmentOut <= std_logic_vector(unsigned(SegmentIn)-1);
    else
      SegmentOut <= SegmentIn;
    end if;
  end process;
  --Debug <= Temp;
  DataOut <= temp(7 downto 0);
end Behavioral;

A = + 12, B = + 4.            A = + 4, B = – 12
А = 0.1100                    A = 0.0100
В = 0.0100                    B = 1.0100
    ------                        ------
C   1.0000                    C   1.1000
As = Bs, Cs = 1 – overflow    As != Bs - not overflow.

SegmentOut <= unsigned(SegmentIn) + 1 when (not Addend(7) and temp(7));
SegmentOut <= unsigned(SegmentIn) - 1 when (Addend(7) and temp(7));

Addend(7) DataIn(7) temp(7)| Carry Borrow
0         0         0      | 0     0
0         0         1      | 1     0
1         0         0      | 0     0
1         0         1      | 0     1

SegmentOut <= unsigned(signed(SegmentIn) + signed(Addend(7) & Addend(7) & Addend(7) & Addend(7) & Addend(7) & Addend(7) & Addend(7) & "1")) when (temp(7) and CarryFlag);