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  1. How to design a simple Adder with separate carry and borrow flags?
  2. entity carryover is
  3.   port(
  4.     DataIn: in std_logic_vector(7 downto 0);
  5.     SegmentIn: in std_logic_vector(7 downto 0);
  6.     Addend: in std_logic_vector(7 downto 0); --How much to increase DataIn by (as a signed number). Believe it or not, that's the actual word for what we need.
  7.     DataOut: out std_logic_vector(7 downto 0);
  8.     SegmentOut: out std_logic_vector(7 downto 0);
  9.    );
  10. end carryover;
  11.  
  12. architecture Behavioral of carryover is
  13.   signal temp: std_logic_vector(8 downto 0);
  14. begin
  15.   --treat as unsigned because it doesn't actually matter for addition and just make carry and borrow correct
  16.   temp <= std_logic_vector(unsigned("0" & DataIn) + (unsigned)Addend);
  17.   DataOut <= temp(7 downto 0);
  18.   SegmentOut <= unsigned(SegmentIn) + 1 when (not temp(8)) and (not Addend(7)
  19.  
  20. end Behavioral;
  21.    
  22. library IEEE;
  23. use IEEE.STD_LOGIC_1164.ALL;
  24. use IEEE.NUMERIC_STD.ALL;
  25. use work.tinycpu.all;
  26.  
  27. entity carryover is
  28.   port(
  29.     EnableCarry: in std_logic; --When disabled, SegmentIn goes to SegmentOut
  30.     DataIn: in std_logic_vector(7 downto 0);
  31.     SegmentIn: in std_logic_vector(7 downto 0);
  32.     Addend: in std_logic_vector(7 downto 0); --How much to increase DataIn by (as a signed number). Believe it or not, that's the actual word for what we need.
  33.     DataOut: out std_logic_vector(7 downto 0);
  34.     SegmentOut: out std_logic_vector(7 downto 0)
  35. --    Debug: out std_logic_vector(8 downto 0)
  36.    );
  37. end carryover;
  38.  
  39. architecture Behavioral of carryover is
  40.   signal temp: std_logic_vector(8 downto 0);
  41. begin
  42.   --treat as unsigned because it doesn't actually matter for addition and just make carry and borrow correct
  43.   process(DataIn, SegmentIn,Addend, EnableCarry)
  44.   begin
  45.     temp <= std_logic_vector(signed('0' & DataIn) + signed(Addend(7) & Addend));
  46.     if (EnableCarry and ((not Addend(7)) and (DataIn(7)) and temp(8)))='1' then
  47.       SegmentOut <= std_logic_vector(unsigned(SegmentIn)+1);
  48.     elsif (EnableCarry and (Addend(7) and (not DataIn(7)) and temp(8)))='1' then
  49.       SegmentOut <= std_logic_vector(unsigned(SegmentIn)-1);
  50.     else
  51.       SegmentOut <= SegmentIn;
  52.     end if;
  53.   end process;
  54.   --Debug <= Temp;
  55.   DataOut <= temp(7 downto 0);
  56. end Behavioral;
  57.    
  58. A = + 12, B = + 4.            A = + 4, B = – 12
  59. А = 0.1100                    A = 0.0100
  60. В = 0.0100                    B = 1.0100
  61.     ------                        ------  
  62. C   1.0000                    C   1.1000
  63. As = Bs, Cs = 1 – overflow    As != Bs - not overflow.
  64.    
  65. SegmentOut <= unsigned(SegmentIn) + 1 when (not Addend(7) and temp(7));
  66. SegmentOut <= unsigned(SegmentIn) - 1 when (Addend(7) and temp(7));
  67.    
  68. Addend(7) DataIn(7) temp(7)| Carry Borrow
  69. 0         0         0      | 0     0
  70. 0         0         1      | 1     0
  71. 1         0         0      | 0     0
  72. 1         0         1      | 0     1
  73.    
  74. SegmentOut <= unsigned(signed(SegmentIn) + signed(Addend(7) & Addend(7) & Addend(7) & Addend(7) & Addend(7) & Addend(7) & Addend(7) & "1")) when (temp(7) and CarryFlag);
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