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ddr4 mig

Dec 31st, 2018
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  1.  
  2.  
  3. /******************************************************************************
  4. // (c) Copyright 2013 - 2014 Xilinx, Inc. All rights reserved.
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  49. ******************************************************************************/
  50. //   ____  ____
  51. //  /   /\/   /
  52. // /___/  \  /    Vendor             : Xilinx
  53. // \   \   \/     Version            : 1.0
  54. //  \   \         Application        : DDR4
  55. //  /   /         Filename           : ddr4_0.v
  56. // /___/   /\     Date Last Modified : $Date: 2014/09/03 $
  57. // \   \  /  \    Date Created       : Thu Apr 18 2013
  58. //  \___\/\___\
  59. //
  60. // Device           : UltraScale
  61. // Design Name      : DDR4_SDRAM
  62. // Purpose          :
  63. //   Wrapper module for the user design top level file. This module can be
  64. //   instantiated in the system and interconnect as shown in example design
  65. //   (example_top module).
  66. // Reference        :
  67. // Revision History :
  68. //*****************************************************************************
  69.  
  70. `timescale 1ns/1ps
  71. (* CORE_GENERATION_INFO = "DDR4_SDRAM, DDR4_SDRAM,{x_ipProduct=Vivado 2017.2.0,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=DDR4_SDRAM,x_ipVersion=2.2, Controller_Type = DDR4_SDRAM, Time_Period = 750, Input_Clock_Period = 13501, Memory_Type = Components, Memory_Part = MT40A1G8PM-075E, Ecc = true, Cas_Latency = 18, Cas_Write_Latency = 14, DQ_Width = 72, Chip_Select = true, Data_Mask = NO_DM_NO_DBI, MEM_ADDR_ORDER = ROW_COLUMN_BANK,  Is_AXI_Enabled = true , Slot_cofiguration =  Single , Clamshell_cofiguration =  false ,IS_FASTER_SPEED_RAM = No, Is_custom_part = false, Memory_Voltage = 1.2V, Phy_Only = Complete_Memory_Controller, Debug_Port = Disable, Burst_Length = 8, System_Clock = Differential, AXI_Selection = true, AXI_Data_Width = 512,  AXI_ArbitrationScheme = RD_PRI_REG, AXI_Narrow_Burst = false, Simulation_Mode = BFM, Debug_Mode = Disable, Example_TG = SIMPLE_TG, Self_Refresh = false, Save_Restore = false, MicroBlaze_ECC = false,  Specify_MandD = false, CLKBOUT_MULT = 18, DIVCLK_DIVIDE = 1, CLKOUT0_DIVIDE = 4}" *)
  72. (* X_CORE_INFO = "ddr4_v2_2_5,Vivado 2018.2" *)
  73. module ddr4_0
  74.    (
  75.    input  sys_rst,
  76.  
  77.    input                 c0_sys_clk_p,
  78.    input                 c0_sys_clk_n,
  79.  
  80.  
  81.    output                c0_ddr4_act_n,
  82.    output [16:0]          c0_ddr4_adr,
  83.    output [1:0]          c0_ddr4_ba,
  84.    output [1:0]          c0_ddr4_bg,
  85.    output [0:0]          c0_ddr4_cke,
  86.    output [0:0]          c0_ddr4_odt,
  87.    output [0:0]          c0_ddr4_cs_n,
  88.    output [0:0]               c0_ddr4_ck_t,
  89.    output [0:0]               c0_ddr4_ck_c,
  90.    output                c0_ddr4_reset_n,
  91.    inout  [8:0]          c0_ddr4_dm_dbi_n,
  92.    inout  [71:0]          c0_ddr4_dq,
  93.    inout  [8:0]         c0_ddr4_dqs_c,
  94.    inout  [8:0]         c0_ddr4_dqs_t,
  95.  
  96.    output                c0_init_calib_complete,
  97.    output                c0_ddr4_ui_clk,
  98.    output                c0_ddr4_ui_clk_sync_rst,
  99.    output               dbg_clk,
  100.  
  101.     // AXI CTRL port
  102.     input                              c0_ddr4_s_axi_ctrl_awvalid,
  103.     output                             c0_ddr4_s_axi_ctrl_awready,
  104.     input  [31:0]                      c0_ddr4_s_axi_ctrl_awaddr,
  105.     // Slave Interface Write Data Ports
  106.     input                              c0_ddr4_s_axi_ctrl_wvalid,
  107.     output                             c0_ddr4_s_axi_ctrl_wready,
  108.     input  [31:0]                      c0_ddr4_s_axi_ctrl_wdata,
  109.     // Slave Interface Write Response Ports
  110.     output                             c0_ddr4_s_axi_ctrl_bvalid,
  111.     input                              c0_ddr4_s_axi_ctrl_bready,
  112.     output [1:0]                       c0_ddr4_s_axi_ctrl_bresp,
  113.     // Slave Interface Read Address Ports
  114.     input                              c0_ddr4_s_axi_ctrl_arvalid,
  115.     output                             c0_ddr4_s_axi_ctrl_arready,
  116.     input  [31:0]                      c0_ddr4_s_axi_ctrl_araddr,
  117.     // Slave Interface Read Data Ports
  118.     output                             c0_ddr4_s_axi_ctrl_rvalid,
  119.     input                              c0_ddr4_s_axi_ctrl_rready,
  120.     output [31:0]                      c0_ddr4_s_axi_ctrl_rdata,
  121.     output [1:0]                       c0_ddr4_s_axi_ctrl_rresp,
  122.  
  123.     // Interrupt output
  124.     output                             c0_ddr4_interrupt,
  125.    // Slave Interface Write Address Ports
  126.    input                 c0_ddr4_aresetn,
  127.    input  [3:0]      c0_ddr4_s_axi_awid,
  128.    input  [32:0]    c0_ddr4_s_axi_awaddr,
  129.    input  [7:0]                       c0_ddr4_s_axi_awlen,
  130.    input  [2:0]                       c0_ddr4_s_axi_awsize,
  131.    input  [1:0]                       c0_ddr4_s_axi_awburst,
  132.    input  [0:0]                       c0_ddr4_s_axi_awlock,
  133.    input  [3:0]                       c0_ddr4_s_axi_awcache,
  134.    input  [2:0]                       c0_ddr4_s_axi_awprot,
  135.    input  [3:0]                       c0_ddr4_s_axi_awqos,
  136.    input                              c0_ddr4_s_axi_awvalid,
  137.    output                             c0_ddr4_s_axi_awready,
  138.    // Slave Interface Write Data Ports
  139.    input  [511:0]    c0_ddr4_s_axi_wdata,
  140.    input  [63:0]  c0_ddr4_s_axi_wstrb,
  141.    input                              c0_ddr4_s_axi_wlast,
  142.    input                              c0_ddr4_s_axi_wvalid,
  143.    output                             c0_ddr4_s_axi_wready,
  144.    // Slave Interface Write Response Ports
  145.    input                              c0_ddr4_s_axi_bready,
  146.    output [3:0]      c0_ddr4_s_axi_bid,
  147.    output [1:0]                       c0_ddr4_s_axi_bresp,
  148.    output                             c0_ddr4_s_axi_bvalid,
  149.    // Slave Interface Read Address Ports
  150.    input  [3:0]      c0_ddr4_s_axi_arid,
  151.    input  [32:0]    c0_ddr4_s_axi_araddr,
  152.    input  [7:0]                       c0_ddr4_s_axi_arlen,
  153.    input  [2:0]                       c0_ddr4_s_axi_arsize,
  154.    input  [1:0]                       c0_ddr4_s_axi_arburst,
  155.    input  [0:0]                       c0_ddr4_s_axi_arlock,
  156.    input  [3:0]                       c0_ddr4_s_axi_arcache,
  157.    input  [2:0]                       c0_ddr4_s_axi_arprot,
  158.    input  [3:0]                       c0_ddr4_s_axi_arqos,
  159.    input                              c0_ddr4_s_axi_arvalid,
  160.    output                             c0_ddr4_s_axi_arready,
  161.    // Slave Interface Read Data Ports
  162.    input                              c0_ddr4_s_axi_rready,
  163.    output [3:0]      c0_ddr4_s_axi_rid,
  164.    output [511:0]    c0_ddr4_s_axi_rdata,
  165.    output [1:0]                       c0_ddr4_s_axi_rresp,
  166.    output                             c0_ddr4_s_axi_rlast,
  167.    output                             c0_ddr4_s_axi_rvalid,
  168.  
  169.    // Debug Port
  170.    output wire [511:0]             dbg_bus
  171.    );
  172.  
  173.  
  174. ddr4_0_ddr4
  175.    inst (
  176.    .sys_rst           (sys_rst),
  177.  
  178.    .c0_sys_clk_p                   (c0_sys_clk_p),
  179.    .c0_sys_clk_n                   (c0_sys_clk_n),
  180.  
  181.    .c0_init_calib_complete (c0_init_calib_complete),
  182.    .c0_ddr4_act_n          (c0_ddr4_act_n),
  183.    .c0_ddr4_adr            (c0_ddr4_adr),
  184.    .c0_ddr4_ba             (c0_ddr4_ba),
  185.    .c0_ddr4_bg             (c0_ddr4_bg),
  186.    .c0_ddr4_cke            (c0_ddr4_cke),
  187.    .c0_ddr4_odt            (c0_ddr4_odt),
  188.    .c0_ddr4_cs_n           (c0_ddr4_cs_n),
  189.    .c0_ddr4_ck_t           (c0_ddr4_ck_t),
  190.    .c0_ddr4_ck_c           (c0_ddr4_ck_c),
  191.    .c0_ddr4_reset_n        (c0_ddr4_reset_n),
  192.    .c0_ddr4_dm_dbi_n       (c0_ddr4_dm_dbi_n),
  193.    .c0_ddr4_dq             (c0_ddr4_dq),
  194.    .c0_ddr4_dqs_c          (c0_ddr4_dqs_c),
  195.    .c0_ddr4_dqs_t          (c0_ddr4_dqs_t),
  196.    .c0_ddr4_ui_clk                (c0_ddr4_ui_clk),
  197.    .c0_ddr4_ui_clk_sync_rst       (c0_ddr4_ui_clk_sync_rst),
  198.    .addn_ui_clkout1                            (),
  199.    .addn_ui_clkout2                            (),
  200.    .addn_ui_clkout3                            (),
  201.    .addn_ui_clkout4                            (),
  202.    .dbg_clk                                    (dbg_clk),
  203.    .sl_iport0                                  (37'b0),
  204.    .sl_oport0                                  (),
  205.  
  206.    // AXI CTRL port
  207.    .c0_ddr4_s_axi_ctrl_awvalid                     (c0_ddr4_s_axi_ctrl_awvalid),
  208.    .c0_ddr4_s_axi_ctrl_awready                     (c0_ddr4_s_axi_ctrl_awready),
  209.    .c0_ddr4_s_axi_ctrl_awaddr                      (c0_ddr4_s_axi_ctrl_awaddr),
  210.    // Slave Interface Write Data Ports
  211.    .c0_ddr4_s_axi_ctrl_wvalid                      (c0_ddr4_s_axi_ctrl_wvalid),
  212.    .c0_ddr4_s_axi_ctrl_wready                      (c0_ddr4_s_axi_ctrl_wready),
  213.    .c0_ddr4_s_axi_ctrl_wdata                       (c0_ddr4_s_axi_ctrl_wdata),
  214.    // Slave Interface Write Response Ports
  215.    .c0_ddr4_s_axi_ctrl_bvalid                      (c0_ddr4_s_axi_ctrl_bvalid),
  216.    .c0_ddr4_s_axi_ctrl_bready                      (c0_ddr4_s_axi_ctrl_bready),
  217.    .c0_ddr4_s_axi_ctrl_bresp                       (c0_ddr4_s_axi_ctrl_bresp),
  218.    // Slave Interface Read Address Ports
  219.    .c0_ddr4_s_axi_ctrl_arvalid                     (c0_ddr4_s_axi_ctrl_arvalid),
  220.    .c0_ddr4_s_axi_ctrl_arready                     (c0_ddr4_s_axi_ctrl_arready),
  221.    .c0_ddr4_s_axi_ctrl_araddr                      (c0_ddr4_s_axi_ctrl_araddr),
  222.    // Slave Interface Read Data Ports
  223.    .c0_ddr4_s_axi_ctrl_rvalid                      (c0_ddr4_s_axi_ctrl_rvalid),
  224.    .c0_ddr4_s_axi_ctrl_rready                      (c0_ddr4_s_axi_ctrl_rready),
  225.    .c0_ddr4_s_axi_ctrl_rdata                       (c0_ddr4_s_axi_ctrl_rdata),
  226.    .c0_ddr4_s_axi_ctrl_rresp                       (c0_ddr4_s_axi_ctrl_rresp),
  227.    // Interrupt output
  228.    .c0_ddr4_interrupt                              (c0_ddr4_interrupt),
  229.    .c0_ddr4_aresetn                                (c0_ddr4_aresetn),
  230.    // Slave Interface Write Address Ports
  231.    .c0_ddr4_s_axi_awid                             (c0_ddr4_s_axi_awid),
  232.    .c0_ddr4_s_axi_awaddr                           (c0_ddr4_s_axi_awaddr),
  233.    .c0_ddr4_s_axi_awlen                            (c0_ddr4_s_axi_awlen),
  234.    .c0_ddr4_s_axi_awsize                           (c0_ddr4_s_axi_awsize),
  235.    .c0_ddr4_s_axi_awburst                          (c0_ddr4_s_axi_awburst),
  236.    .c0_ddr4_s_axi_awlock                           (c0_ddr4_s_axi_awlock),
  237.    .c0_ddr4_s_axi_awcache                          (c0_ddr4_s_axi_awcache),
  238.    .c0_ddr4_s_axi_awprot                           (c0_ddr4_s_axi_awprot),
  239.    .c0_ddr4_s_axi_awqos                            (c0_ddr4_s_axi_awqos),
  240.    .c0_ddr4_s_axi_awvalid                          (c0_ddr4_s_axi_awvalid),
  241.    .c0_ddr4_s_axi_awready                          (c0_ddr4_s_axi_awready),
  242.    // Slave Interface Write Data Ports
  243.    .c0_ddr4_s_axi_wdata                            (c0_ddr4_s_axi_wdata),
  244.    .c0_ddr4_s_axi_wstrb                            (c0_ddr4_s_axi_wstrb),
  245.    .c0_ddr4_s_axi_wlast                            (c0_ddr4_s_axi_wlast),
  246.    .c0_ddr4_s_axi_wvalid                           (c0_ddr4_s_axi_wvalid),
  247.    .c0_ddr4_s_axi_wready                           (c0_ddr4_s_axi_wready),
  248.    // Slave Interface Write Response Ports
  249.    .c0_ddr4_s_axi_bid                              (c0_ddr4_s_axi_bid),
  250.    .c0_ddr4_s_axi_bresp                            (c0_ddr4_s_axi_bresp),
  251.    .c0_ddr4_s_axi_bvalid                           (c0_ddr4_s_axi_bvalid),
  252.    .c0_ddr4_s_axi_bready                           (c0_ddr4_s_axi_bready),
  253.    // Slave Interface Read Address Ports
  254.    .c0_ddr4_s_axi_arid                             (c0_ddr4_s_axi_arid),
  255.    .c0_ddr4_s_axi_araddr                           (c0_ddr4_s_axi_araddr),
  256.    .c0_ddr4_s_axi_arlen                            (c0_ddr4_s_axi_arlen),
  257.    .c0_ddr4_s_axi_arsize                           (c0_ddr4_s_axi_arsize),
  258.    .c0_ddr4_s_axi_arburst                          (c0_ddr4_s_axi_arburst),
  259.    .c0_ddr4_s_axi_arlock                           (c0_ddr4_s_axi_arlock),
  260.    .c0_ddr4_s_axi_arcache                          (c0_ddr4_s_axi_arcache),
  261.    .c0_ddr4_s_axi_arprot                           (c0_ddr4_s_axi_arprot),
  262.    .c0_ddr4_s_axi_arqos                            (c0_ddr4_s_axi_arqos),
  263.    .c0_ddr4_s_axi_arvalid                          (c0_ddr4_s_axi_arvalid),
  264.    .c0_ddr4_s_axi_arready                          (c0_ddr4_s_axi_arready),
  265.    // Slave Interface Read Data Ports
  266.    .c0_ddr4_s_axi_rid                              (c0_ddr4_s_axi_rid),
  267.    .c0_ddr4_s_axi_rdata                            (c0_ddr4_s_axi_rdata),
  268.    .c0_ddr4_s_axi_rresp                            (c0_ddr4_s_axi_rresp),
  269.    .c0_ddr4_s_axi_rlast                            (c0_ddr4_s_axi_rlast),
  270.    .c0_ddr4_s_axi_rvalid                           (c0_ddr4_s_axi_rvalid),
  271.    .c0_ddr4_s_axi_rready                           (c0_ddr4_s_axi_rready),
  272.    // Debug Port
  273.    .dbg_bus               (dbg_bus)
  274.    );
  275.  
  276.  endmodule
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