`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 10.03.2020 15:03:02
// Design Name:
// Module Name: draw_rect
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////


module draw_rect(
    input wire [10:0] hcount_in,
    input wire hsync_in,
    input wire hblnk_in,
    input wire [10:0] vcount_in,
    input wire vsync_in,
    input wire vblnk_in,
    input wire [11:0] rgb_in,
    input wire [11:0] xpos,
    input wire [11:0] ypos,
    input wire [11:0] rgb_pixel,    //
    input wire pclk,

    output reg [10:0] hcount_out,
    output reg hsync_out,
    output reg hblnk_out,
    output reg [10:0] vcount_out,
    output reg vsync_out,
    output reg vblnk_out,
    output reg [11:0] rgb_out,
    output reg [11:0] pixel_address  //
    );

    wire [5:0] addry, addrx;

    reg [10:0] hcount_temp;
    reg hsync_temp;
    reg [10:0] vcount_temp;
    reg vsync_temp;
    reg vblnk_temp;
    reg hblnk_temp;

    reg [11:0] rgb_out_nxt  = 0;

    localparam
        X_WIDTH = 48,
        Y_HEIGHT = 64;

    always @*
       if((hcount_in > (xpos + 1)) && (hcount_in < (xpos + X_WIDTH + 2))  &&
           (vcount_in >= ypos) && (vcount_in <= (ypos + Y_HEIGHT - 1))) begin
              rgb_out_nxt = rgb_pixel;
              end
       else begin
            rgb_out_nxt = rgb_in;
            end

    always @(posedge pclk)
    begin
      rgb_out <= rgb_out_nxt;
      pixel_address <= {addry[5:0], addrx[5:0]};

      hcount_temp <= hcount_in;
      hsync_temp <= hsync_in;
      vcount_temp <= vcount_in;
      vsync_temp <= vsync_in;
      vblnk_temp <= vblnk_in;
      hblnk_temp <= hblnk_in;

      hcount_out <= hcount_temp;
      hsync_out <= hsync_temp;
      vblnk_out <= vblnk_temp;
      vcount_out <= vcount_temp;
      vsync_out <= vsync_temp;
      hblnk_out <= hblnk_temp;
  end

     assign addry = vcount_in - ypos;
     assign addrx = hcount_in - xpos;

endmodule