module top;
    logic clock, reset, serial, isNew;
    logic [7:0] messageByte;
    logic [16:0] counter;

    Receiver recv(.clock, .reset, .serialIn(serial), .isNew, .messageByte);
    Sender   send(.clock, .reset, .serialOut(serial));

    initial begin
        $monitor($time,, "%b  || %c %b | %b %b | %d %b %s", serial, recv.messageByte, recv.messageByte, recv.is1BitErr, recv.is2BitErr, recv.bitPos, recv.inCode, recv.currState.name);

        @(posedge clock)
        reset = 0;
        @(posedge clock)
        reset = 1;
        @(posedge clock)
        reset = 0;

    end

    initial begin
        counter = 0;
        clock = 0;
        forever #5 begin
            clock = ~clock;
            counter = counter + 1;

            if (counter > 5000)
                $finish;
        end
    end
endmodule: top


module Receiver
     (input  logic       clock, reset, serialIn,
      output logic [7:0] messageByte,
      output logic       isNew);

    logic keepCounting, startOver;
    logic en, clear;
    logic getCode, clearCode;
    logic Cout;
    logic is1BitErr, is2BitErr;
    logic haveError;
    logic [3:0] nextBitPos, bitPos, syndrome;
    logic [12:0] inCode, outCode, shifted;
    logic [7:0]  decodedBin, storeCode;

    logic atEnd;

    Adder #(4)     adder(.A(bitPos), .B(4'd1), .Cin(1'd0), .Cout, .S(nextBitPos));
    register #(4)  counter(.en(keepCounting), .clear(startOver), .D(nextBitPos), .Q(bitPos), .clock);
    register #(8)  decode(.en(getCode), .clear(clearCode), .Q(messageByte), .D(storeCode), .clock);
    register #(13) code(.en, .clear, .D(shifted), .Q(inCode), .clock);
    SECDEDdecoder  SECDEDd(.inCode, .syndrome, .is1BitErr, .is2BitErr, .outCode);
    codeToNumber   cTN(.inCode(outCode), .outNum(decodedBin));

    enum logic [1:0] {START, RECV, DONE, ERROR} currState, nextState;

    assign atEnd = (bitPos == 'd14);
    assign storeCode = (haveError) ? 'd15 : decodedBin;
    assign shifted = (inCode << 1) | (serialIn && currState == RECV);

    always_comb begin
        getCode = 0;
        clearCode = 0;
        nextState = START;
        keepCounting = 0;
        startOver = 0;
        isNew = 0;
        haveError = 0;
        en = 0;
        clear = 0;

        unique case (currState)
            START: begin
                if (serialIn) begin
                    nextState = RECV;
                    en = 1;
                    keepCounting = 1;
                end else begin
                    nextState = START;
                    clear = 1;
                    startOver = 1;
                end
            end
            RECV: begin
                if (atEnd == 0) begin
                    nextState = RECV;
                    en = 1;
                    keepCounting = 1;
                end else begin
                    getCode = 1;
                    isNew = 1;
                    if (is2BitErr == 0 && serialIn == 0) begin
                        nextState = DONE;
                        haveError = 0;
                    end else begin
                        nextState = ERROR;
                        haveError = 1;
                    end
                end
            end
            DONE: begin
                nextState = START;
                clear = 1;
                startOver = 1;
            end
            ERROR: begin
                nextState = START;
                clear = 1;
                startOver = 1;
            end
        endcase
    end

    always_ff @(posedge clock, posedge reset) begin
        if (reset) currState <= START;
        else currState <= nextState;
    end
endmodule: Receiver;

module codeToNumber
    (input logic [12:0] inCode,
     output logic [7:0] outNum);

    assign outNum[0] = inCode[3];
    assign outNum[3:1] = inCode[7:5];
    assign outNum[7:4] = inCode[12:9];

endmodule: codeToNumber;