MM VRU Running dASM

80088AB0	0x9AB0	send or jam (A2) msg A1 to queue A0
80088C00
80088DA0	0x9DA0	800991AC = 0
80088DB0
80088E70	0x9E70	read or wait (A2) to write msg from queue A0 to A1
80088FB0

800890B0	0xA0B0	V0 = errors when sending Shift-JIS string A1 to VRU using handle A0
	accepts: A0=p->VRU handle, A1=p->Shift-JIS string
	v = call 800936D0(@A0+0, @A0+4, SP+4B)	# V0 = error state for status of controller ports A1 on, writing status flags to A2
	if v:
		return v
	if SP[4B] & 2:	# Err 0xF if Slot Empty set
		return 0xF
	l = 0
	while A1[l]:
		l += 2
	call 8008A5D0(SP+20, 0x28)	# initialize A1 bytes at A0
	# 80089134: byteswap data, aligned to the right side of the buffer
	v = 0x27 - l
	for i in range(0, l, 2):
		SP[v+i+1] = A1[i]
		SP[v+i] = A1[i+1]
	# 8008917C
	if l >= 0xF:
		v = call 80091E10(@A0+0, @A0+4, 0, SP+20)	# V0 = error state when sending SI cmd 0xA writing data A3 to VRU address A2 on port A1, informing queue A0
		if v:
			return v
	v = call 80091E10(@A0+0, @A0+4, 0, SP+34)	# V0 = error state when sending SI cmd 0xA writing data A3 to VRU address A2 on port A1, informing queue A0
	if v:
		return v
	v = call 8008A520(A0, SP+4B)	# V0 = errors when reading controller status to A1 and and set VRU state in handle A0
	if not v:
		return 0
	elif v & 0x100:
		return 0xD	# VRU buffer overflow
	elif v & 0x200:
		return 0xE	# invalid word
	elif v & 0xFF00:
		return 5
	return v
80089240

8008A520	0xB520	V0 = errors when reading controller status to A1 and and set VRU state in handle A0
	accepts: A0=p->VRU handle, A1=p->controller status flags
	v = call 800936D0(@A0+0, @A0+4, A1)	# V0 = error state for status of controller ports A1 on, writing status flags to A2
	if v:
		return v
	if A1[0] & 1:	# Err 0xF if Slot Filled set
		return 0xF
	v = call 8008FE70(@A0+0, @A0+4, 0, SP+20)	# V0 = error state when sending SI cmd 0xB reading data from VRU address A2 on port A1 to A3, informing queue A0
	if v:
		return v
	A0[C] = SP[20] & 7	# state
	if SP[20] & 0x40:
		return 0xF
	return SP[21] << 8
8008A5D0	0xB5D0	initialize A1 bytes at A0

8008A670	0xB670	write controller pak with rumble yada yada...
8008A7D8	0xB7D8	rumble pak yada yada...
8008A8E4

8008AA40	0xBA40	create message queue 8009EAB8
	80098E60 = True
	call 800901E0(8009EAB8, 8009EAB0, 1)	# create msg queue A0 with A2 msgs at A1
	call 80088AB0(8009EAB8, 0, False)	# send or jam (A2) msg A1 to queue A0
8008AA90	0xBA90	wait for msg on queue 8009EAB8, creating queue if necessary
	if not @80098E60:
		call 8008AA40()	# create message queue 8009EAB8
	call 80088E70(8009EAB8, SP+1C, True)	# read or wait (A2) to write msg from queue A0 to A1
8008AAD4	0xBAD4	send msg 0 to queue 8009EAB8
	call 80088AB0(8009EAB8, 0, True)	# send or jam (A2) msg A1 to queue A0
8008AB00

8008AF30	0xBF30	V0 = error state when sending SI cmd 1 reading controllers
	accepts: A0=p->queue
	call 8008AA90()	# wait for msg on queue 8009EAB8, creating queue if necessary
	if 8009EB10[0] != 1:
		call 8008B040()	# fill buffer 8009EAD0 with SI status or reset (A0) commands
		call 8008BD10(1, 8009EAD0)	# read or write (A0) between rdram A1 and pifram
		call 80088E70(A0, 0, True)	# read or wait (A2) to write msg from queue A0 to A1
	# 8008AF7C
	v = call 8008BD10(0, 8009EAD0)	# read or write (A0) between rdram A1 and pifram
	call 80088E70(A0, 0, True)	# read or wait (A2) to write msg from queue A0 to A1
	return v
8008AFB4
8008B040	0xC040	fill buffer 8009EAD0 with SI status or reset (A0) commands
8008B110	0xC110	V0 = error state when writing VRU listening results to A1 using handle A0
	accepts: A0=p->VRU handle, A1=p->target
	if @A0+8 not in range(1,5):
		return 5
	if @A0+8 == 1:
		# 8008B15C
		v = call 800936D0(@A0+0, @A0+4, SP+5F)	# V0 = error state for status of controller ports A1 on, writing status flags to A2
		if v:
			return v
		if SP[5F] & 1:
			return 0xC
		v = call 8008FE70(@A0+0, @A0+4, 0, SP+38)	# V0 = error state when sending SI cmd 0xB reading data from VRU address A2 on port A1 to A3, informing queue A0
		if v:
			return v
		A0[C] = SP[38] & 7
		8009EB60[0] = SP[38] & 7
		if A0[C] not in (0, 7):
			return 0xC
	if @A0+8 in (1, 2):
		# 8008B1D8
		A0+8 = 2
		v = call 800936D0(@A0+0, @A0+4, SP+5F)	# V0 = error state for status of controller ports A1 on, writing status flags to A2
		if v:
			return v
		if SP[5F] & 2:	# Err 0xF if Slot Empty set
			return 0xF
		SP+38 = 0x600
		v = call 80097500(@A0+0, @A0+4, 0, SP+38)	# V0 = error state when sending SI cmd 0xC with data A3 to VRU address A2, informing queue A0
		if v:
			return v
	if @A0+8 in (1, 2, 3):
		# 8008B240
		A0+8 = 3
		v = call 800936D0(@A0+0, @A0+4, SP+5F)	# V0 = error state for status of controller ports A1 on, writing status flags to A2
		if v:
			return v
		if SP[5F] & 1:	# Err 0xF if Slot Filled set
			return 0xF
		v = call 80090770(@A0+0, @A0+4, 0, SP+38)	# V0 = error state when sending SI cmd 9 reading data from VRU address A2 on port A1 to A3, informing queue A0
		if v:
			return v
		A1[0:2] = (SP[3D] << 8) + SP[3C]	# error flags
		A1[2:4] = SP[3E]			# number of valid results
		A1[4:6] = (SP[41] << 8) + SP[40]	# mic voice level
		A1[6:8] = (SP[43] << 8) + SP[42]	# voice level relative to noise
		A1[8:A] = (SP[45] << 8) + SP[44]	# voice length
		for i in range(0, 0x14, 4):	# not really a loop, but less confusing this way for comparison's sake
			A1[A+i:C+i] = (SP[47+i] << 8) + SP[46+i]
			A1[14+i:16+i] = (SP[49+i] << 8) + SP[48+i]
		# 8008B400
		if A1[A:C] == 0x7FFF:	# when no hits, ensure no results listed
			A1[2:4] = 0
		A0[C] = SP[5A] & 7
		if not 8009EB60[0] or not A0[C]:
			A0+8 = 0
			return v
	if @A0+8 in (1, 2, 3, 4):
		# 8008B42C
		A0+8 = 4
		v = call 800936D0(@A0+0, @A0+4, SP+5F)	# V0 = error state for status of controller ports A1 on, writing status flags to A2
		if v:
			return v
		if SP[5F] & 1:	# Err 0xF if Slot Filled set
			return 0xF
		v = call 8008FE70(@A0+0, @A0+4, 0, SP+38)	# V0 = error state when sending SI cmd 0xB reading data from VRU address A2 on port A1 to A3, informing queue A0
		if v:
			return v
		A0[C] = SP[38] & 7
		if A0[C]:
			return 0xF
		return v
8008B4E0

8008BD10	0xCD10	read or write (A0) between rdram A1 and pifram
8008BDC0

8008FCD0	0x10CD0	V0 = errors when clearing A1 strings from VRU using handle A0
	accepts: A0=p->VRU handle, A1=#strings
	v = call 800936D0(@A0+0, @A0+4, SP+2B)	# V0 = error state for status of controller ports A1 on, writing status flags to A2
	if v:
		return v
	if SP[2B] & 2:	# Err 0xF if Slot Empty set
		return 0xF
	SP+24 = 0x2000000 | (A1 << 8)
	v = call 80097500(@A0+0, @A0+4, 0, SP+24)	# V0 = error state when sending SI cmd 0xC with data A3 to VRU address A2, informing queue A0
	if v:
		return v
	v = call 8008A520(A0, SP+2B)	# V0 = errors when reading controller status to A1 and and set VRU state in handle A0
	if v & 0xFF00:
		return 5
	return v
8008FD80

8008FE70	0x10E70	V0 = error state when sending SI cmd 0xB reading data from VRU address A2 on port A1 to A3, informing queue A0
	accepts: A0=p->queue, A1=controller slot, A2=address, A3=p->target
	call 8008AA90()	# wait for msg on queue 8009EAB8, creating queue if necessary
	for i in range(2, 0, -1):
		if @8009EB10 != 0xB or @80098FE0 != A1:
			8009EB10 = 0xB
			80098FE0 = A1
			800A01D0[:A1] = repeat(0, A1)
			800A01D0[3C] = 1
			800A01D0[A1] = 0xFF
			800A01D0[A1+1] = 3
			800A01D0[A1+2] = 3
			800A01D0[A1+3] = 0xB
			800A01D0[A1+8] = 0xFF
			800A01D0[A1+9] = 0xFE
		# 8008FF88
		800A01D0[A1+4] = A2 >> 3
		v = call 80092040(A2)	# V0 = controller pak address checksum for A0
		800A01D0[A1+5] = (A2 << 5) | v
		call 8008BD10(1, 800A01D0)	# read or write (A0) between rdram A1 and pifram
		call 80088E70(A0, 0, True)	# read or wait (A2) to write msg from queue A0 to A1
		call 8008BD10(0, 800A01D0)	# read or write (A0) between rdram A1 and pifram
		call 80088E70(A0, 0, True)	# read or wait (A2) to write msg from queue A0 to A1
		# 8008FFE0
		v = (800A01D0[A1+2] & 0xC0) >> 4
		if v:
			v = 1
			break
		crc = call 800900A0(800A01D0+A1+6, 2)	# V0 = controller pak data checksum for A1 bytes at A0
		if crc != 800A01D0[A1+8]:
			v = call 800936D0(A0, A1, SP+10)	# V0 = error state for status of controller ports A1 on, writing status flags to A2
			if v:
				break
			v = 4
		else:
			call 80092260(800A01D0+A1+6, A3, 2)	V0 = p->A2 bytes copied from A0 to A1
		if v != 4:
			break
	# 8009005C
	call 8008AAD4()	# send msg 0 to queue 8009EAB8
	return v
800900A0	V0 = controller pak data checksum for A1 bytes at A0
	accepts: A0=p->data, A1=length
80090140	0x11140	V0 = p->char A1 in string A0 else None
80090180	0x11180	V0 = strlen(A0)
800901A8	0x111A8	copy string A1 to A0
800901E0	0x111E0	create msg queue A0 with A2 msgs at A1
80090210

80090770	0x11770	V0 = error state when sending SI cmd 9 reading data from VRU address A2 on port A1 to A3, informing queue A0
	accepts: A0=p->msg queue, A1=initial controller port, A2=address, A3=p->target
	call 8008AA90()	# wait for msg on queue 8009EAB8, creating queue if necessary
	for i in range(2, 0, -1):
		if 8009EB10[0] != 9 or @80098FE0 != A1:
			8009EB10 = 9
			80098FE0 = A1
			800A01D0[:A1] = repeat(0, A1)
			800A01D0[3C] = 1
			800A01D0[A1] = 0xFF
			800A01D0[A1+1] = 3
			800A01D0[A1+2] = 0x25
			800A01D0[A1+3] = 9
			800A01D0[A1+2A] = 0xFF
			800A01D0[A1+2B] = 0xFE
		# 80090888
		800A01D0[A1+4] = A2 >> 3
		v = call 80092040(A2)	# V0 = controller pak address checksum for A0
		800A01D0[A1+5] = (A2 << 5) | v
		call 8008BD10(1, 800A01D0)	# read or write (A0) between rdram A1 and pifram
		call 80088E70(A0, 0, True)	# read or wait (A2) to write msg from queue A0 to A1
		call 8008BD10(0, 800A01D0)	# read or write (A0) between rdram A1 and pifram
		call 80088E70(A0, 0, True)	# read or wait (A2) to write msg from queue A0 to A1
		# 800908D0
		f = (800A01D0[A1+2] & 0xC0) >> 4
		if f:
			f = 1
		else:
			v = call 800900A0(800A01D0[A1+6], 0x24)	# V0 = controller pak data checksum for A1 bytes at A0
			if v == 800A01D0[A1+2A]:
				call 80092260(800A01D0[A1+6], A3, 0x24)	# V0 = p->A2 bytes copied from A0 to A1
			else:
				f = call 800936D0(A0, A1, SP+10)	# V0 = error state for status of controller ports A1 on, writing status flags to A2
				if f:
					break
				f = 4
		if f != 4:
			break
	call 8008AAD4()	# send msg 0 to queue 8009EAB8
	return f
800909A0

80091670	0x12670	initialize VRU and read current state
	accepts: A0=p->queue, A1=p->VRU handle, A2=controller slot
	A1+0 = A0	# p->queue
	A1+4 = A2	# controller slot
	A1+8 = 0	# mode
	SP[37] = 0
	v = call 800936D0(A0, A2, SP+37)	# V0 = error state for status of controller ports A1 on, writing status flags to A2
	if v:
		return v
	v = call 800917B0(A0, A2)	# sends SI cmd 0xFD to controller slot A1, informing queue A0
	if v:
		return 4
	# 800916DC
	for i in range(5):	# addresses, >> 3 actual: (0x1E, 0x6E, 8, 0x56, 3)
		v = call 800918A0(A0, A2, 80098FD0[i])	# send 0xD cmd with address A2 to VRU controller slot A1, informing queue A0
		if v:
			return v
	# 80091710
	v = call 800936D0(A0, A2, SP+37)	# V0 = error state for status of controller ports A1 on, writing status flags to A2
	if v:
		return v
	if SP[37] & 2:
		return 0xF	# Err 0xF if Slot Empty set
	SP+30 = 0x100
	v = call 80097500(A0, A2, 0, SP+30)	# V0 = error state when sending SI cmd 0xC with data A3 to VRU address A2, informing queue A0
	if v:
		return v
	v = call 8008A520(A1, SP+37)	# V0 = errors when reading controller status to A1 and and set VRU state in handle A0
	if v & 0xFF00:
		return 5
	return v
800917B0	0x127B0	sends SI cmd 0xFD to controller slot A1, informing queue A0
	accepts: A0=p->queue, A1=controller slot
	call 8008AA90()	# wait for msg on queue 8009EAB8, creating queue if necessary
	800A01D0+3C = True
	800A01D0[0:A1] = repeat(0, A1)
	800A01D0[A1] = 0xFD
	800A01D0[A1 + 1] = 0xFE
	call 8008BD10(1, 800A01D0)	# read or write (A0) between rdram A1 and pifram
	call 80088E70(A0, 0, True)	# read or wait (A2) to write msg from queue A0 to A1
	v = call 8008BD10(0, 800A01D0)	# read or write (A0) between rdram A1 and pifram
	call 80088E70(A0, 0, True)	# read or wait (A2) to write msg from queue A0 to A1
	call 8008AAD4()	# send msg 0 to queue 8009EAB8
	return v
800918A0	0x128A0	V0 = error state when sending SI cmd 0xD with address A2 to VRU controller slot A1, informing queue A0
	accepts: A0=p->queue, A1=controller slot, A2=address
	call 8008AA90()	# wait for msg on queue 8009EAB8, creating queue if necessary
	for i in range(2, 0, -1):
		if 8009EB10[0] != 0xD or @80098FE0 != A1:
			8009EB10[0] = 0xD
			80098FE0 = A1
			800A01D0[0:A1] = repeat(0, A1)
			800A01D0[A1] = 3
			800A01D0[A1+1] = 1
			800A01D0[A1+2] = 0xD
			800A01D0[A1+5] = 0
			800A01D0[A1+6] = 0xFE
			800A01D0+3C = 1
		# 800919A4
		800A01D0[A1+3] = A2
		800A01D0[A1+4] = call 80092040(A2 << 3)	# V0 = controller pak address checksum for A0
		call 8008BD10(1, 800A01D0)	# read or write (A0) between rdram A1 and pifram
		call 80088E70(A0, 0, True)	# read or wait (A2) to write msg from queue A0 to A1
		call 8008BD10(0, 800A01D0)	# read or write (A0) between rdram A1 and pifram
		call 80088E70(A0, 0, True)	# read or wait (A2) to write msg from queue A0 to A1
		f = 800A01D0[A1+1] & 0xC0
		f >>= 4
		if f:
			f = 1
			# autopasses through test at 80091A34
			break
		if 800A01D0[A1+5] & 1:
			f = call 800936D0(A0, A1, SP+10)	# V0 = error state for status of controller ports A1 on, writing status flags to A2
			if f:
				call 8008AAD4()	# send msg 0 to queue 8009EAB8
				return f
			f = 4
		# 80091A34
		if f != 4:
			break
	# 80047C5C
	call 8008AAD4()	# send msg 0 to queue 8009EAB8
	return f
80091A90

80091BE0	0x12BE0	V0 = error state when sending SI cmd 2 with address A2 to controller slot A1, informing queue A0
	accepts: A0=p->queue, A1=controller slot, A2=address
	# Read controller slot cmd.
	call 8008AA90()	# wait for msg on queue 8009EAB8, creating queue if necessary
	for i in range(2, 0, -1):
		if 8009EB10[0] != 2 or @80098FE0 != A1:
			8009EB10[0] = 2
			80098FE0 = A1
			800A01D0[0:A1] = repeat(0, A1)
			800A01D0[A1] = 3
			800A01D0[A1+1] = 0x21
			800A01D0[A1+2] = 0x2
			800A01D0[A1+25] = 0xFF
			800A01D0[A1+26] = 0xFE
		# 80091CF8
		800A01D0[A1+4] = A2 >> 3
		v = call 80092040(A2)	# V0 = controller pak address checksum for A0
		800A01D0[A1+5] = (A2 << 5) | v
		call 8008BD10(1, 800A01D0)	# read or write (A0) between rdram A1 and pifram
		call 80088E70(A0, 0, True)	# read or wait (A2) to write msg from queue A0 to A1
		call 8008BD10(0, 800A01D0)	# read or write (A0) between rdram A1 and pifram
		call 80088E70(A0, 0, True)	# read or wait (A2) to write msg from queue A0 to A1
		# 80091D50
		f = (800A01D0[A1+2] & 0xC0) >> 4
		if f:
			f = 1
		else:
			crc = call 80092110(800A01D0[A1+6])	# V0 = controller pak data checksum for A0
			if crc == 800A01D0[A1+25]:
				call 80092260(A0, A1, 0x20)	# V0 = p->A2 bytes copied from A0 to A1
			else:
				f = call 8008C360(A0, A1)
				if f:
					break
				f = 4
		if f != 4:
			break
	call 8008AAD4()	# send msg 0 to queue 8009EAB8
	return f
80091E10	0x12E10	V0 = error state when sending SI cmd 0xA writing data A3 to VRU address A2 on port A1, informing queue A0
	accepts: A0=p->queue, A1=controller port, A2=address, A3=p->data
	call 8008AA90()	# wait for msg on queue 8009EAB8, creating queue if necessary
	for i in range(2, 0, -1):
		if @8009EB10 != 0xA and @80098FE0 != A1:
			8009EB10 = 0xA
			80098FE0 = A1
			800A01D0[:A1] = repeat(0, A1)
			800A01D0[3C] = 1
			800A01D0[A1] = 0xFF
			800A01D0[A1+1] = 0x17
			800A01D0[A1+2] = 1
			800A01D0[A1+3] = 0xA
			800A01D0[A1+1A] = 0xFF
			800A01D0[A1+1B] = 0xFE
		# 80091F28
		800A01D0[A1+4] = A2 >> 3
		v = call 80092040(A2)	# V0 = controller pak address checksum for A0
		800A01D0[A1+5] = (A2 << 5) | v
		call 80092260(A3, 800A01D0+A1+6, 0x14)	# V0 = p->A2 bytes copied from A0 to A1
		call 8008BD10(1, 800A01D0)	# read or write (A0) between rdram A1 and pifram
		crc = call 800900A0(A3, 0x14)	# V0 = controller pak data checksum for A1 bytes at A0
		call 80088E70(A0, 0, True)	# read or wait (A2) to write msg from queue A0 to A1
		call 8008BD10(0, 800A01D0)	# read or write (A0) between rdram A1 and pifram
		call 80088E70(A0, 0, True)	# read or wait (A2) to write msg from queue A0 to A1
		f = (800A01D0[A1+2] & 0xC0) >> 4
		if f:
			f = 1
			break
		if 800A01D0[A1+1A] != crc:
			f = call 800936D0(A0, A1, SP+10)	# V0 = error state for status of controller ports A1 on, writing status flags to A2
			if f:
				break
			f = 4
		if f != 4:
			break
	# 800561FC
	call 8008AAD4()	# send msg 0 to queue 8009EAB8
	return f
80092040	0x13040	V0 = controller pak address checksum for A0
80092110	0x13110	V0 = controller pak data checksum for A0
800921B0	0x131B0	V0 = @80098E4C
800921C0

80092260	0x13260	V0 = p->A2 bytes copied from A0 to A1

80093260	0x14260	V0 = errors when sending VRU cmd 7 and testing state
	accepts: A0=p->VRU handle
	v = call 800936D0(@A0+0, @A0+4, SP+3F)	# V0 = error state for status of controller ports A1 on, writing status flags to A2
	if v:
		return v
	if SP[3F] & 2:
		return 0xF	# Err 0xF if Slot Empty set
	if not @A0+8:
		return 5
	SP+38 = 0x700
	v = call 80097500(@A0+0, @A0+4, 0, SP+38)	# V0 = error state when sending SI cmd 0xC with data A3 to VRU address A2, informing queue A0
	if not v:
		# 800932F0
		for i in range(0x14):
			v = call 8008A520(A0, SP+3F)	# V0 = errors when reading controller status to A1 and and set VRU state in handle A0
			if not v & 0xFF00:
				A0+8 = 0
			elif not v & 7:
				v = 0
				A0+8 = 0
			elif (v & 7) == 7:
				v = 5
			else:
				A0+8 = 0
			if v != 0xF:
				break
		SP+40 = i
	# 80093358
	return v
80093380
800933E0	0x143E0	initialize and read controller presence flags to A1, informing queue A0
	accepts: A0=p->msg queue, A1=p->presence flags
	call 8008AA90()	# wait for msg on queue 8009EAB8, creating queue if necessary
	f = 0
	for i in range(3, 0, -1):
		call 8009356C(0)
		call 8008BD10(1, 800A01D0)	# read or write (A0) between rdram A1 and pifram
		call 80088E70(A0, SP+68, True)	# read or wait (A2) to write msg from queue A0 to A1
		SP+6C = call 8008BD10(0, 800A01D0)	# read or write (A0) between rdram A1 and pifram
		call 80088E70(A0, SP+68, True)	# read or wait (A2) to write msg from queue A0 to A1
		call 80093620(SP+67, SP+54)	# copy result of SI status request to A1, setting presence flags to A0
		...
	# 80093528
	call 8008AAD4()	# send msg 0 to queue 8009EAB8
	A1[0] = f
8009356C	0x1456C	fill buffer 800A01D0 with SI status or reset (A0) commands
	accepts: A0=command (0 or -1)
80093620	copy result of SI status request to A1, setting presence flags to A0
	accepts: A0=p->flags, A1=p->results
800936D0	0x146D0	V0 = error state for status of controller ports A1 on, writing status flags to A2
	accepts: A0=p->msg queue, A1=initial controller port, A2=status flags
	call 8008AA90()	# wait for msg on queue 8009EAB8, creating queue if necessary
	f = 0
	for i in range(2, 0, -1):
		if f != 4:
			8009EAD0+3C = 1
			for j in range(A1):
				8009EAD0[j] = 0
			8009EAD0[j:j+2] = (1, 3)
			j += 2
			8009EAD0[j] = 0
			8009EAD0[j+6] = 0xFE
			8009EB10[0] = 0xFE
			call 8008BD10(1, 8009EAD0)	# read or write (A0) between rdram A1 and pifram
			call 80088E70(A0, 0, True)	# read or wait (A2) to write msg from queue A0 to A1
		# 800937BC
		call 8008BD10(0, 8009EAD0)	# read or write (A0) between rdram A1 and pifram
		call 80088E70(A0, 0, True)	# read or wait (A2) to write msg from queue A0 to A1
		SP[60:66] = 8009EAD0[A1:A1+6]
		f = (SP[61] & 0xC0) >> 4
		A2[0] = SP[65]
		if f:
			f = 1 if f & 8 else 4
		elif SP[63] or SP[64] != 1:
			f = 0xB
		elif SP[65] & 4:
			f = 4
		if f != 4:
			break
	# 80093878
	call 8008AAD4()	# send msg 0 to queue 8009EAB8
	return f
800938C0

80093C20	0x14C20
	accepts: A0=controller port
	call 8008AA90()	# wait for msg on queue 8009EAB8, creating queue if necessary
	8009EB10[1] = max(A0, 4)
	8009EB10[0] = 0xFE
	call 8008AAD4()	# send msg 0 to queue 8009EAB8
80093C80

80093EA0	0x14EA0	???; manages controller pak read and write requests, but beyond the scope of what I'm doing now
	accepts: A0=p->queue, A1, A2=controller slot
	call 8008AA90()	# wait for msg on queue 8009EAB8, creating queue if necessary
	f = call 8008C360(A0, A2)
	call 8008AAD4()	# send msg 0 to queue 8009EAB8
	A1+4 = A0
	if f:
		return f
	A1+0 = 0
	A1+8 = A2
	f = call 800940A8()
	if f:
		return f
	f = call 80093BA0(A1, 0)
	if f:
		return f
	f = call 80091BE0(@A1+4, @A1+8, 1, SP+48)	# V0 = error state when sending SI cmd 2 with address A2 to controller slot A1, informing queue A0
	call 8008D754(SP+48, SP+6A, SP+68)
	...
800940A8

80094D60	0x15D60	V0 = error state when sending SI cmd 3 with data A3 to address A2 on port A1, informing queue A0
	accepts: A0=p->queue, A1=controller slot, A2=addy (11 bits), A3=p->data
	# Controller pak write.
80094FB0	write word A2 to hardware offset A1 using EPI handle A0
80095110

800965B0	0x175B0	V0 = @80098E54
800965C0	0x175C0	V0 = errors when sending A2 bytes of data A1 to VRU using handle A0
	accepts: A0=p->VRU handle, A1=p->data, A2=length
	v = call 800936D0(@A0+0, @A0+4, SP+3B)	# V0 = error state for status of controller ports A1 on, writing status flags to A2
	if v:
		return v
	if SP[3B] & 2:	# Err 0xF if Slot Empty set
		return 0xF
	A2 += A2 & 1	# LE HW alignment
	call 8008A5D0(SP+24, 0x14)	# initialize A1 bytes at A0
	SP[0x36 - A2] = 4
	v = A2 + (A2 & 1)
	for i in range(0, A2, 2):
		addr = i + 0x14 - v
		SP[24+addr] = A1[i]
		SP[25+addr] = A1[i+1]
	if A2 & 1:
		SP[37] = 0
	# 80096698
	v = call 80091E10(@A0+0, @A0+4, 0, SP+10)	# V0 = error state when sending SI cmd 0xA writing data A3 to VRU address A2 on port A1, informing queue A0
	if v:
		return v
	v = call 8008A520(A0, SP+3B)	# V0 = errors when reading controller status to A1 and and set VRU state in handle A0
	if v & 0xFF00:
		return 5
	return v
80096700

80097320	0x18320	???; VRU initialization for specific memory banks...
	accepts: A0=p->VRU handle, A1=bool, A2=index
	v = 0x98 if A1 else 0x18
	v = call 800918A0(@A0+0, @A0+4, v)	# send 0xD cmd with address A2 to VRU controller slot A1, informing queue A0
	if v:
		return v
	if not 0 <= A2 < 8:
		return 5
	v = 800991B0[A2] + 2
	v &= 0xFF
	call 800918A0(@A0+0, @A0+4, v)	# send 0xD cmd with address A2 to VRU controller slot A1, informing queue A0
800973D0	0x183D0	V0 = error state when sending VRU cmd 5 (stop listening) using VRU handle A0
	accepts: A0=p->VRU handle
	v = call 800936D0(@A0+0, @A0+4, SP+2B)	# V0 = error state for status of controller ports A1 on, writing status flags to A2
	if v:
		return v
	if SP[2B] & 2:	# Err 0xF if Slot Empty set
		return 0xF
	if @A0+8:
		return 5
	SP+24 = 0x5000000
	v = call 80097500(@A0+0, @A0+4, 0, SP+24)	# V0 = error state when sending SI cmd 0xC with data A3 to VRU address A2, informing queue A0
	if v:
		return v
	v = call 8008A520(A0, SP+2B)	# V0 = errors when reading controller status to A1 and and set VRU state in handle A0
	if v & 0xFF00:
		return 5
	A0+8 = 1
	return v
80097490

80097500	0x18500	V0 = error state when sending SI cmd 0xC with data A3 to VRU address A2 on port A1, informing queue A0
	accepts: A0=p->queue, A1=controller slot, A2=addy (11 bits), A3=p->data
	call 8008AA90()	# wait for msg on queue 8009EAB8, creating queue if necessary
	for i in range(2, 0, -1):
		if 8009EB10[0] != 0xC and @80098FE0 != A1:
			# 80097570
			8009EB10[0] = 0xC
			80098FE0 = A1
			800A01D0[:A1] = repeat(0, A1)
			800A01D0+3C = 1
			800A01D0[A1] = 0xFF
			800A01D0[A1+1] = 7
			800A01D0[A1+2] = 1
			800A01D0[A1+3] = 0xC
			800A01D0[A1+A] = 0xFF
			800A01D0[A1+B] = 0xFE
		# 80097618
		800A01D0[A1+4] = A2 >> 3
		v = call 80092040(A2)	# V0 = controller pak address checksum for A0
		800A01D0[A1+5] = (A2 << 5) | v
		call 80092260(A3, 800A01D0+A1+6, 4)	# V0 = p->A2 bytes copied from A0 to A1
		call 8008BD10(1, 800A01D0)	# read or write (A0) between rdram A1 and pifram
		crc = call 800900A0(A3, 4) & 0xFF	# V0 = controller pak data checksum for A1 bytes at A0
		call 80088E70(A0, 0, True)	# read or wait (A2) to write msg from queue A0 to A1
		call 8008BD10(0, 800A01D0)	# read or write (A0) between rdram A1 and pifram
		call 80088E70(A0, 0, True)	# read or wait (A2) to write msg from queue A0 to A1
		v = 800A01D0[A1+2] & 0xC0
		v >>= 4
		if v:
			v = 1
		elif 800A01D0[A1+A] != crc:
			# 800976A4
			v = call 800936D0(A0, A1, SP+6B)	# V0 = error state for status of controller ports A1 on, writing status flags to A2
			if not v:
				v = 4
		# 800976D4
		if v != 4:
			break
	# 800976E8
	call 8008AAD4()	# send msg 0 to queue 8009EAB8
	return v
80097730

80098FD0	0x19FD0	VRU init addresses; >> 3 for actual
	1E 6E 08 56 03
80098FD8

800991B0	0x1A1B0	VRU addresses, unknown purpose; >> 3 for actual
	00 80 40 C0 20 A0 60 E0
800991B8

+_+

801138A8
	accepts: A0
	...
	# 80114100
	f = A0[20:22]
	if not (f nor ~0x4000):
		# 80114118
		A0[1CA5] &= ~4
		A0[169C8][224:226] = 0
		A0[169C8][222:224] = A0[169C8][224:226]
		SP+30 = 1
		801BA6E4[0:2] = 0
		# goto 8011450C
	else:
		if not (f nor ~0x8000) or call 801A0060() == 1:	# If A button or most recent, best VRU hit == 1
			# 80114174
			...
		# goto 8011450C
	...
8011455C

801707A4	V0 = p->controller queue
	v = @801CBCE0
	call 80088E70(v+4C, SP+1C, True)	# read or wait (A2) to write msg from queue A0 to A1
	return @SP+1C
801707D8	identical to 801707A4
8017080C	write response from controller queue to A0
	accepts: A0=p->target
	v = @801CBCE0
	call 80088AB0(v+4C, A0, True)	# send or jam (A2) msg A1 to queue A0
8017083C	identical to 801707A4
8017086C

80171158	initialize all connected VRU
	j = @801CBCE0
	for i in range(j[2C8]):	# for controllers connected...
		if j[2C9+i] == 4:
			v = call 801707A4()	# V0 = p->controller queue
			f = call 80091670(v, 801FD708, i)	# initialize VRU and read current state
			call 8017080C(v)	# response from controller queue
			if not f:	# if no errors...
				j[2C9 + i] = 5	# set to a "normal" controller type to avoid reinit
				801CBCE8 = 2	# always run this, in case you need to reinit later
				call 8019FE10()	# unconditional return
	# 80171230
	if @801CBCE8 == 1:
		801CBCE8 = 0
8017127C	compile a table of controller types
	v = @801CBCE0
	f = 0	# flags for "real" controllers
	# 801712D4
	for i in range(4):
		c = v + (i << 2)
		if not c[17]:	# no error
			kind = c[14:16] & 0x1F07
			if kind == 2:	# mouse
				# 80171334
				if not v[2C9+i]:
					v[2C9+i] = 3
			elif kind == 5:	# controller
				# 80171314
				f |= 1 << i
				if not v[2C9+i]:
					v[2C9+i] = 1
			elif kind == 0x100:	# VRU
				# 8017134C
				if not v[2C9+i]:
					v[2C9+i] = 4
					v[2CD+i] = 0
			else:
				# 80171370
				if not v[2C9+i]:
					v[2C9+i] = 0xFF
		else:
			# 80171388
			if v[2C9+i]:
				if v[2C9+i] == 1:	# weird conditional there
					v[2CD+i] = 0
					v[2D5+i] = 0xFF
					v[2C9+i] = 0
				else:
					v[2C9+i] = 0
	# 801713C4
	v+0 = f
801713E4
	SP+1C = call 801707A4()	# V0 = p->controller queue
	call 8008AF30(@SP+1C)	# V0 = error state when sending SI cmd 1 reading controllers
	v = @801CBCE0
	if @v+4:
		call @v+4(@v+8)
	call 80088E70(@SP+1C, 0, True)	# read or wait (A2) to write msg from queue A0 to A1
	call 8008AFB4(v+2B0)
	call 8008A5D0(v+2B6, 0x12)	# initialize A1 bytes at A0
	if v[47E]:
		call 8008A5D0(v+2B0, 0x18)	# initialize A1 bytes at A0
	# 8017146C
	call 8008E6D0(@SP+1C)
	call 80088E70(@SP+1C, 0 True)	# read or wait (A2) to write msg from queue A0 to A1
	call 8008E74C(v+14)
	call 8017080C(@SP+1C)	# response from controller queue
	call 8017127C()	# compile a table of controller types
	call 8017086C()
	call 80170F40()
	if @v+C:
		call @v+C(@v+10)
	# 801714D8
	if @801CBCE8:
		call 80171158()	# initialize all connected VRU
	if 8009E84D[0]:
		call 80170B34()
	else:
		if v[47C] > 0:
			v[47C] -= 1
			call 80170B34()
		elif not v[47D]:
			call 80170B34()
		elif not v[47E]:
			call 801708CC()
			v[47D] -= 1
	# 80171580
	801CBCE4 += 1
801715A0

8018E8C8
	accepts: A0, A1=p->args
	v = 801F0DC0[7878] << 3
	801F0DC0+79F4+v = A0
	801F0DC0+79F4+v+4 = @A1+0
	801F0DC0[7878] += 1
	if 801F0DC0[7878] == 801F0DC0[7879]:
		801F0DC0[7878] -= 1
8018E914	call 8018E8C8(A0, p->A1)
	accepts: A0, A1
8018E938	same as 8018E914()
	accepts: A0, A1
8018E95C	call 8018E8C8(A0, p->(A1 << 0x18))
	accepts: A0, A1
8018E98C	call 8018E8C8(A0, p->(A1 << 0x10))
	accepts: A0, A1
8018E9BC

8018ED18
	v = call 80088E70(@80208748, SP+18, False)	# read or wait (A2) to write msg from queue A0 to A1
	if v == -1:
		return 0
	if 80205209[0] == @SP+18:
		return 1
	else:
		return -1
8018ED70

80199118
	v = call 801A4648()
	if v:
		return
	v = call 801A470C()
	if v:
		return
	call 80198968()
	call 80198704()
	call 801A0078()	# ???; listens for and provides VRU word results
	call 8019B108(801FD3B8)
	call 8019B108(801FD3C8)
	call 8019B488()
	call 8019D700()
	call 8019E08C()
	call 8019AEF8()
	call 8019CE00()
	call 8019C900()
	call 8019D058()
	call 8019EA20()
	call 8019C2AC()
	call 8019F424()
	call 801A2670()
	call 801A38B0()	# execute commands in table at 801FFE90
	call 801A27CC()
	call 801A3C3C()
	call 8019A31C()
	call 8018E9BC()
80199200	NERFED; saves A0 to the stack
80199208	NERFED; saves A0, A1 to the stack
80199214

8019F840
	accepts: A0, A1
	A0 &= 0xFFFF
	A1 &= 0xFFFF
	call 801A3888(0x74000001)
	call 801A3888(0x74040000 | A0 >> 8)
	call 801A3888(0x74050000 | A0 & 0xFF)
	call 801A3AB0(0, 0, 0x7F, 1)
	v = call 801A3930(4)
	if call 801A3930(4) != 0xFFFF and call 801A3930(4) != 1:
		call 801A2BE4(4, 0)
		call 8018E938(0xF8000000, 0)
	# 8019F8F0
	if call 801A3930(3): == 0x81A:
		call 801A3AB0(0, 3, 0x7F, 1)
	call 801A3888(0x4000001)
	for i in range(0x10):
		# 8019F930
		j = (1 << i)
		if A1 & j or A0 & j:
			call 801A3888(0x84010001 | i << 8)
8019F988

8019FCB0
	call 8019FBB4(1)
	call 8018E938(0xF2FF0000, 1)
	call 8018E9BC()
	call 8018E938(0xF8000000, 0)
	801FD528[0] = 0
	801D0EAC[0] = 0
	801FD4FE[0] = 0
8019FD04
	call 8019FCB0()
	v = 801D5C04[0]
	if v < 0xA:
		v = @801D6060+(v<<2)
		call 8018E938(0xE6000100, v + 0x18)
8019FD54	???; sends VRU strings, unmasking the 2nd and 6th word
	accepts: A0 (unused)
	801D5C08[0] = 1
	call 8019F434()
	call 80199068()
	call 8019A090()
	call 801A4898()
	call 801A289C()
	call 8019FF38()	# send VRU strings at 801D3310, unmasking the 2nd and 6th word
	if 801D5C04[0] == 0xB:
		call 801A0B20(0x6F)	# set values in table 801FFDD4 based on mask A0
8019FDC4
	call 801A4898()
	call 8018E938(0xF2FF0000, 1)
	call 8019F434()
	call 8019A090()
	call 8019FBB4(1)
	call 8019FF38()	# send VRU strings at 801D3310, unmasking the 2nd and 6th word
8019FE10	unconditional return
8019FE18	send VRU strings at 801D3310 with masks set on for all
	if 801D356C[0]:	# if turned "on", turn "off" to send data
		q = call 801707D8()	# V0 = p->controller queue
		call 80093260(801FD708)	# V0 = errors when sending VRU cmd 7 and testing state
		call 8017083C(@q+0)	# write response from controller queue to A0
	# 8019FE58
	v = call 801A0424()	# V0 = p->VRU data buffer
	i = 0
	while i <= 0:
		SP[38+i] = v[0+i]
		i += 1
	v = call 801A0188(801D3310)	# send strings at A0 to VRU
	if v:
		return v
	for i in range(6):
		# 8019FEA0
		j = i >> 3
		if i < 0:	# which it can't be
			j = (i + 7) >> 3
		k = i & 7
		if i < 0 and k:	# which it still can't be
			k -= 8
		if (SP[38+j] >> k) & 1:
			call 801A0430(i)	# set and update VRU word mask for entry A0
	# 8019FEF8
	call 801A0348(0x320, 2, 0x400, 0x1F4, 0x7D0)	# set VRU threshold levels
	801D356C[0] = 1	# turn "on"
8019FF38	send VRU strings at 801D3310, unmasking the 2nd and 6th word
	call 801A0430(-1)	# set and update VRU word mask for entry A0
	if not 801D356C[0]:	# return if turned "off"
		return
	q = call 801707D8()	# V0 = p->controller queue
	call 80093260(801FD708)	# V0 = errors when sending VRU cmd 7 and testing state
	call 8017083C(@q+0)	# write response from controller queue to A0
	e = call 801A0188(801D3310)	# send strings at A0 to VRU
	call 801A0430(-1)	# set and update VRU word mask for entry A0
	# 8019FF90
	if not e:
		call 801A0348(0x320, 2, 0x400, 0x1F4, 0x7D0)	# set VRU threshold levels
		801D356C[0] = 1	# turn "on"
	# 8019FFC0
	call 8019FFE0(5)	# if turned "on", unset and update VRU word mask for entry A0
	call 8019FFE0(1)	# if turned "on", unset and update VRU word mask for entry A0
8019FFE0	if turned "on", unset and update VRU word mask for entry A0
	accepts: A0=index
	if not 801D356C[0]:	# turned "off"
		return
	if A0 < 6:
		call 801A05E0(A0)	# unset and update VRU word mask for entry A0
801A0020	if turned "on", set VRU string mask for word A0
	accepts: A0=index
	if not 801D356C[0]:	# turned "off"
		return
	if A0 < 6:
		call 801A0430(A0)	# set and update VRU word mask for entry A0
801A0060	V0 = most recent, best VRU hit; V0 = 801D3574[0:2]
801A006C	V0 = VRU mode flags; 801D356C[0]
801A0078	???; listens for and provides VRU word results
	if 801D356C[0] & 2:	# if tacit, send strings and masks
		801D356C[0] &= 1
		call 8019FE18()	# send VRU strings at 801D3310 with masks set on for all
	if not 801D356C[0]:	# return if turned "off"
		return
	v = call 801A0768()	# listen for registered set of VRU words and fetch results
	if v:
		# 801A00BC
		801D3578[0] += 1
		801D3578[0] &= 0xFF
		if 801D3578[0] == 0xA:
			801D356C[0] = 0	# turn "off"
			801D3574[0:2] = -1
			return
	else:
		# 801A00F4
		801D3578[0] = 0
	# 801A0100
	v = call 801A02F0()	# V0=p->VRU results; pop @801FD6F0+8, send VRU cmd 5
	801D3570 = v	# p->most recent VRU results
	if not v:
		801D3574[0:2] = -1
	else:
		801D3574[0:2] = v[A:C]	# first, best hit
801A0150	V0 = -1 if VRU error A0 in (1, 4, 5, 11, 13, 14, 15) else 0
	accepts: A0=VRU error state
	A0 -= 1
	# if A0 < 0xF:
	# 	call @801DF5FC+(A0<<2)()
	if A0 in (0, 3, 4, A, C, D, E)
		# 801A0174
		return -1
	else:
		return 0
801A0188	send strings at A0 to VRU
	accepts: A0=p->string pointers
	801FD6F0[4] = 0
	801FD6F0+8 = 0	# NULL pointer to VRU results
	801FD6F0[C:E] = 0x3E8	# deviance threshold
	801FD6F0[E:10] = 5	# maximum acceptable results
	801FD6F0[10:12] = 0	# error flag mask
	801FD6F0+0 = A0
	ctrl = @801FD6F0+0
	q = call 801707D8()	# V0 = p->controller queue
	e = call 8008FCD0(801FD708, ctrl[258])	# V0 = errors when clearing A1 strings from VRU using handle A0
	call 8017083C(q)	# write response from controller queue to A0
	if e:
		return e
	# 801A0218
	v = ctrl[258] - 1	# count - 1
	if v < 7:
		v += 7
	v >>= 3	# SRA
	v += 1
	for i in range(v):
		801FD758[i] = 0
	# 801A0258
	for i in range(ctrl[258]):
		q = call 801707D8()	# V0 = p->controller queue
		v = A0 + (i * 0x1E)
		e = call 800890B0(801FD708, v)	# V0 = errors when sending Shift-JIS string A1 to VRU using handle A0
		call 8017083C(q)	# write response from controller queue to A0
		if call 801A0150(e):	# V0 = -1 if VRU error A0 in (1, 4, 5, 11, 13, 14, 15) else 0
			call 801A097C(v)	# write SJIS string A0 phonetically to 801FD760
	return e
801A02F0	V0=p->VRU results; pop @801FD6F0+8, send VRU cmd 5
	v = @801FD6F0+8
	801FD6F0+8 = 0
	q = call 801707D8()	# V0 = p->controller queue
	call 800973D0(801FD708)	# V0 = error state when sending VRU cmd 5 (stop listening) using VRU handle A0
	call 8017083C(q)	# write response from controller queue to A0
	return v
801A033C	V0 = p->VRU instance; V0 = @801FD6F0+0
801A0348	set VRU threshold levels
	accepts: A0=deviance threshold, A1=maximum #results, A2=error flag mask, A3=minimum voice level from mic, SP+10=minimum relative voice level
	801FD6F0[C:E] = A0
	801FD6F0[E:10] = A1
	801FD6F0[10:12] = A2
	801FD6F0[12:14] = A3
	801FD6F0[14:16] = @SP+10
801A037C
	accepts: A0, A1
	v = @801FD6F0+0
	if not v:
		return
	SP+18 = call 801707D8()	# V0 = p->controller queue
	SP+1C = call 80097320(801FD708, A0, A1)	# ???; VRU initialization for specific memory banks...
	call 8017083C(@SP+18)	# write response from controller queue to A0
	if @SP+1C:
		call 801A0150(@SP+1C)	# V0 = -1 if VRU error A0 in (1, 4, 5, 11, 13, 14, 15) else 0
801A03E8

801A0424	V0 = p->VRU data buffer; V0 = 801FD758
801A0430	set and update VRU word mask for entry A0
	accepts: A0=index
	v = @801FD6F0+0
	A0 &= 0xFFFF
	if v:
		c = 801FD6F0[258]
		f = True
	else:	# if strings aren't present, assume full buffer, create a table, then don't send it.
		c = 0x14
		f = False
	if A0 == 0xFFFF:
		# 801A046C
		for i in range(c):
			j = i + 7 if i < 0 else i	# This can't happen though
			j >>= 3
			k = i & 7
			if i < 0 and k:
				k -= 8
			801FD758[j] |= 1 << k
	else:
		# 801A04DC
		i = A0
		if i < 0:
			i += 7
		i >>= 3
		j = A0 & 7
		if A0 < 0 and j:
			j -= 8
		k = 1 << j
		if 801FD758[i] & k:
			f = False
		else:
			801FD758[i] |= k
	# 801A0530
	if not f:
		return
	SP[22] = c
	SP+1C = call 801707D8()	# V0 = p->controller queue
	SP+24 = call 80093260(801FD708)	# V0 = errors when sending VRU cmd 7 and testing state
	call 8017083C(@SP+1C)	# write response from controller queue to A0
	if @SP+1C and 801FD6F4[0]:
		801FD6F4[0] = 0
		return
	SP+1C = call 801707D8()	# V0 = p->controller queue
	v = c - 1
	if v < 0:
		v += 7
	v >>= 3
	SP+24 = call 800965C0(801FD708, 801FD758, v + 1)	# V0 = errors when sending A2 bytes of data A1 to VRU using handle A0
	call 8017083C(@SP+1C)	# write response from controller queue to A0
	801FD6F4 = 0
801A05E0	unset and update VRU word mask for entry A0
	accepts: A0=index
	v = @801FD6F0
	if not v:
		f, c = False, 0x14
	else:
		f, c = True, v[258]
	if A0 == 0xFFFF:
		# 801A061C
		j = c - 1
		if j < 0:
			j += 7
		j >>= 3
		j += 1
		801FD758[0:j] = repeat(0, j)
	else:
		# 801A0664
		j = A0
		if j < 0:	# this can't happen...
			j += 7
		j >>= 3
		k = A0 & 7
		if A0 < 0 and k:
			k -= 8
		v = 801FD758[j] & (1 << k)
		if not v:
			# if not set, don't update
			f = False
		else:
			# untoggle flag and update
			801FD758[j] &= ~(1 << k)
	# 801A06BC
	if not f:
		return
	SP[22] = c
	SP+1C = call 801707D8()	# V0 = p->controller queue
	SP+24 = call 80093260(801FD708)	# V0 = errors when sending VRU cmd 7 and testing state
	call 8017083C(@SP+1C)	# write response from controller queue to A0
	if @SP+24 and 801FD6F0[4]:
		801FD6F0[4] = 0
		return @SP+24
	j = c - 1
	if j < 0:
		j += 7
	j >>= 3
	j += 1
	SP+1C = call 801707D8()	# V0 = p->controller queue
	SP+24 = call 800965C0(801FD708, 801FD758, j)	# V0 = errors when sending A2 bytes of data A1 to VRU using handle A0
	call 8017083C(@SP+1C)	# write response from controller queue to A0
	801FD6F0[4] = 0
	return @SP+24
801A0768	listen for registered set of VRU words and fetch results
	if 801FD6F0[4] == 0:
		# 801A07A0: stop listening
		SP+1C = call 801707D8()	# V0 = p->controller queue
		SP+24 = call 800973D0(801FD708)	# V0 = error state when sending VRU cmd 5 (stop listening) using VRU handle A0
		call 8017083C(@SP+1C)	# write response from controller queue to A0
		801FD6F4[0] = 1
	elif 801FD6F0[4] == 1:
		# 801A07D4: fetch results
		SP+1C = call 801707D8()	# V0 = p->controller queue
		SP+24 = call 8008B110(801FD708, 801FD718)	# V0 = error state when writing VRU listening results to A1 using handle A0
		call 8017083C(@SP+1C)	# write response from controller queue to A0
		v = call 801A0150(@SP+24)	# V0 = -1 if VRU error A0 in (1, 4, 5, 11, 13, 14, 15) else 0
		if v:
			return v
		# if 801FD714[0] < 8:
		# 	call @801DF638+(801FD714[0]<<2)()
		if 801FD714[0] == 0:
			# 801A0834
			801FD6F0[4] = 2
		elif 801FD714[0] == 7:
			# 801A0844
			801FD6F0[4] = 2
	elif 801FD6F0[4] == 2:
		# 801A0854: verify results and reset
		if not (801FD718[0:2] & 801FD6F0[10:12]):	# error not in mask
			if 801FD718[2:4] <= 801FD6F0[E:10] and	# no more than given number of results
			   801FD718[14:16] <= 801FD6F0[C:E] and	# best hit's deviance below threshold
			   801FD718[4:6] >= 801FD6F0[12:14] and	# above minimum voice level from mic
			   801FD718[6:8] >= 801FD6F0[14:16]:	# voice level relative to noise above minimum
				801FD6F0+8 = 801FD738	# set p->VRU results
				801FD738[0:1E] = 801FD718[0:1E]
		# 801A0908
		SP+1C = call 801707D8()	# V0 = p->controller queue
		call 80093260(801FD708)	# V0 = errors when sending VRU cmd 7 and testing state
		call 8017083C(@SP+1C)	# write response from controller queue to A0
		SP+1C = call 801707D8()	# V0 = p->controller queue
		SP+24 = call 800973D0(801FD708)	# V0 = error state when sending VRU cmd 5 (stop listening) using VRU handle A0
		call 8017083C(@SP+1C)	# write response from controller queue to A0
		801FD6F0[4] = 1
	# 801A0958
	return call 801A0150(@SP+24)	# V0 = -1 if VRU error A0 in (1, 4, 5, 11, 13, 14, 15) else 0
801A0970	reset listening state; 801FD6F0 = 0
801A097C	write SJIS string A0 phonetically to 801FD760
	accepts: A0=p->VRU string
	l = call 80090180(A0)	# V0 = strlen(A0)
	for i in range(0, l, 2):
		SP[28:2A] = A0[i:i+2]
		if SP[28] == 0x83:
			# 801A0A0C: katakana
			v = SP[29] * 3
			801FD760[i] = 801D36A0[v - 0xC0]
			801FD760[i+1] = 801D36A0[v - 0xBF]
		elif SP[28] == 0x82:
			# 801A0A48: hiragana
			v = SP[29] * 3
			801FD760[i] = 801D3580[v - 0x1DD]
			801FD760[i+1] = 801D3580[v - 0x1DC]
		elif SP[28:2A] == 0x815B:	# 'ー'
			# 801A0A88
			801FD760[i:i+2] = 0x2D2D	# "--"
		else:
			# 801A0AB8
			801FD760[i:i+2] = 0x2020	# "  "
		# 801A0AD8
	# 801A0AEC
	801FD760[l] = 0
801A0B20	set values in table 801FFDD4 based on mask A0
	accepts: A0=mask
	for i in range(A0):
		for j in range(8):
			801FFDD4.append(bool(i & 1))
			i >>= 1
801A0B78

801A2C64
	accepts: A0
	cmd = A0 >> 0x1C	# upper nibble
	v = (A0 >> 0x18) & 7
	# if cmd < 0x10:
	# 	call @801DF680+(cmd<<2)(A0, v)
	if cmd == 0:
		# 801A2CAC
		...
	elif cmd == 1:
		# 801A2E30
		...
	elif cmd == 2:
		# 801A2E50
		...
	elif cmd == 3:
		# 801A3020
		...
	elif cmd == 4:
		# 801A3180
		...
	elif cmd == 5:
		# 801A3238
		...
	elif cmd == 0xD:
		# 801A332C
		...
	elif cmd == 6:
		# 801A3404
		...
	elif cmd == 7:
		# 801A3508
		...
	elif cmd == 8:
		# 801A3544
		...
	elif cmd == 9:
		# 801A35D0
		...
	elif cmd == 0xA:
		# 801A35FC
		...
	elif cmd == 0xB:
		# 801A3694
		...
	elif cmd == 0xC:
		# 801A36C0
		...
	elif cmd == 0xE:
		# 801A3760
		...
	elif cmd == 0xF:
		# 801A37EC: VRU
		v = (A0 >> 0x10) & 0xFF
		if not v:
			# 801A3804
			801D5BCC[0] = (A0 >> 8) & 0xFF
			v = 801D5C04[0]
			801D5C04[0] = A0 & 0xFF
			call 8018EDC4()
			call 8019FD54(v)	# ???; sends VRU strings, unmasking the 2nd and 6th word
			call 8018E938(0xF8000000, 0)
		else:
			# 801A384C
			801D5C0C = A0
			80200D1C[0] = 0x14
			80200D1C[2:4] = 0x7FFF
			80200D1C[4:6] = 0x666
	# 801A3874
	return
801A3888	append command A0 to table at 801FFE90
	accepts: A0=command
	v = 801D5BF0[0] << 2
	801FFE90+v = A0
	801D5BF0[0] += 1
801A38B0	execute commands in table at 801FFE90
	while 801D5BF0[4] != 801D5BF0[0]:
		# 801A38EC
		v = 801D5BF0[4] << 2
		801D5BF0[4] += 1
		call 801A2C64(@801FFE90+v)
801A3930
801A399C

801A4648
	v = 801D5C08[0]
	if not v:
		return v
	if v == 1:
		v = call 8018ED18()
		if v == 1:
			801D5C08[0] = 0
			call 8018E95C(0x46020000, 801D5BCC[0])
			call 8019FD04()
		return 801D5C08[0]
	elif v == 2:
		v = call 8018ED18()
		while v != 1:
			call 8018ED18()
		801D5C08[0] = 0
		call 8018E95C(0x46020000, 801D5BCC[0])
		call 8019FD04()
		return 801D5C08[0]
801A470C
801A4898

801D3310	VRU word buffer
	アトナンジカン	atonanjikan	How many hours left	En_Gs			gossip stone
	ハイチーズ		haichīzu	say cheese		(master)		pictograph
	オキロー		okirō		wake up			En_Hidden_Nuts		sleeping Deku Scrub
	オスワリ		osuwari		sit
	ミルク		miruku		milk			En_Cow			cow
	ハイヤー		haiyā		hiya!			En_Horse		Epona
801D3568	+258	number of strings
801D356C[0]	+25C	VRU flags
	xxxxxxx0	turned "off"
	xxxxxxx1	turned "on"
	xxxxxx10	device not ready (indicates you need to send it a word list)
801D3570	+260	p->most recent VRU results or None
801D3574[0:2]	+264	first, best VRU hit or -1 or 0x7FFF

801D3580	phonetic table for hiragana (debug on error)
801D36A0	phonetic table for katakana (debug on error)
801D37C0

801FD6F0	some kind of (very heavy) VRU manager
	+0	801FD6F0	p->VRU instance (801D3310)
	+4	801FD6F4[0]	listening state
	+8	801FD6F8	p->VRU results or NULL
	+C	801FD6FC[0:2]	deviance threshold			{0x320, 0x3E8}
	+E	801FD6FE[0:2]	maximum number of returned results	{2, 5}
	+10	801FD700[0:2]	error flag mask for results		{0x400, 0}
		0400	voice too low; occurs with low voice levels and relative voice levels, unsure rules
		0800	voice too high; any voice level over 0xDAC(?) appears to trigger this
		4000	no valid matches; I think this means the deviation for all results is greater than the default 0x640 seen in software, since can report match results anyway.
		8000	too much noise; relative voice level below 0x190(?) appears to trigger this
	+12	801FD702[0:2]	minimum voice level from mic		{0x1F4}
	+14	801FD704[0:2]	minimum voice level relative to noise	{0x7D0}
	+18	801FD708	p->VRU handle
	+24	801FD714	status (0-7)
	+28	801FD718	listening results buffer; 0x1E
	+48	801FD738	current listening results; 0x1E
	+68	801FD758	data buffer
	+70	801FD760	buffer for phonetic string on transmission error; 0x20
	+90	801FD780

Listening results are ordered a little differently than the actual returned command data.
The VRUs produce signed, little-endian values.  Listening results are big-endian.
Results are reorganized so indices and deviance are grouped.
	0x0	2	error flags
	0x2	2	# valid results (results under "normal" deviance)
	0x4	2	voice level from mic
	0x6	2	voice level relative to noise
	0x8	2	voice length (prob. milliseconds)
	0xA	2	hit 1: index or 0x7FFF
	0xC	2	hit 2: index or 0x7FFF
	0xE	2	hit 3: index or 0x7FFF
	0x10	2	hit 4: index or 0x7FFF
	0x12	2	hit 5: index or 0x7FFF
	0x14	2	hit 1: deviance value
	0x16	2	hit 2: deviance value
	0x18	2	hit 3: deviance value
	0x1A	2	hit 4: deviance value
	0x1C	2	hit 5: deviance value
	0x1E	2	mode + status flags; normally should report 0040