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  1. CPU 0:
  2. vendor_id = "GenuineIntel"
  3. version information (1/eax):
  4. processor type = primary processor (0)
  5. family = Intel Pentium Pro/II/III/Celeron/Core/Core 2/Atom, AMD Athlon/Duron, Cyrix M2, VIA C3 (6)
  6. model = 0x5 (5)
  7. stepping id = 0x1 (1)
  8. extended family = 0x0 (0)
  9. extended model = 0x4 (4)
  10. (simple synth) = Intel Mobile Core i3-4000Y / Mobile Core i5-4000Y / Mobile Core i7-4000Y / Mobile Pentium 3500U/3600U/3500Y / Mobile Celeron 2900U (Mobile U/Y) (Haswell), 22nm
  11. miscellaneous (1/ebx):
  12. process local APIC physical ID = 0x0 (0)
  13. cpu count = 0x10 (16)
  14. CLFLUSH line size = 0x8 (8)
  15. brand index = 0x0 (0)
  16. brand id = 0x00 (0): unknown
  17. feature information (1/edx):
  18. x87 FPU on chip = true
  19. virtual-8086 mode enhancement = true
  20. debugging extensions = true
  21. page size extensions = true
  22. time stamp counter = true
  23. RDMSR and WRMSR support = true
  24. physical address extensions = true
  25. machine check exception = true
  26. CMPXCHG8B inst. = true
  27. APIC on chip = true
  28. SYSENTER and SYSEXIT = true
  29. memory type range registers = true
  30. PTE global bit = true
  31. machine check architecture = true
  32. conditional move/compare instruction = true
  33. page attribute table = true
  34. page size extension = true
  35. processor serial number = false
  36. CLFLUSH instruction = true
  37. debug store = true
  38. thermal monitor and clock ctrl = true
  39. MMX Technology = true
  40. FXSAVE/FXRSTOR = true
  41. SSE extensions = true
  42. SSE2 extensions = true
  43. self snoop = true
  44. hyper-threading / multi-core supported = true
  45. therm. monitor = true
  46. IA64 = false
  47. pending break event = true
  48. feature information (1/ecx):
  49. PNI/SSE3: Prescott New Instructions = true
  50. PCLMULDQ instruction = true
  51. 64-bit debug store = true
  52. MONITOR/MWAIT = true
  53. CPL-qualified debug store = true
  54. VMX: virtual machine extensions = true
  55. SMX: safer mode extensions = false
  56. Enhanced Intel SpeedStep Technology = true
  57. thermal monitor 2 = true
  58. SSSE3 extensions = true
  59. context ID: adaptive or shared L1 data = false
  60. FMA instruction = true
  61. CMPXCHG16B instruction = true
  62. xTPR disable = true
  63. perfmon and debug = true
  64. process context identifiers = true
  65. direct cache access = false
  66. SSE4.1 extensions = true
  67. SSE4.2 extensions = true
  68. extended xAPIC support = true
  69. MOVBE instruction = true
  70. POPCNT instruction = true
  71. time stamp counter deadline = true
  72. AES instruction = true
  73. XSAVE/XSTOR states = true
  74. OS-enabled XSAVE/XSTOR = true
  75. AVX: advanced vector extensions = true
  76. F16C half-precision convert instruction = true
  77. RDRAND instruction = true
  78. hypervisor guest status = false
  79. cache and TLB information (2):
  80. 0x63: data TLB: 1G pages, 4-way, 4 entries
  81. 0x03: data TLB: 4K pages, 4-way, 64 entries
  82. 0x76: instruction TLB: 2M/4M pages, fully, 8 entries
  83. 0xff: cache data is in CPUID 4
  84. 0xb5: instruction TLB: 4K, 8-way, 64 entries
  85. 0xf0: 64 byte prefetching
  86. 0xc1: L2 TLB: 4K/2M pages, 8-way, 1024 entries
  87. processor serial number: 0004-0651-0000-0000-0000-0000
  88. deterministic cache parameters (4):
  89. --- cache 0 ---
  90. cache type = data cache (1)
  91. cache level = 0x1 (1)
  92. self-initializing cache level = true
  93. fully associative cache = false
  94. extra threads sharing this cache = 0x1 (1)
  95. extra processor cores on this die = 0x7 (7)
  96. system coherency line size = 0x3f (63)
  97. physical line partitions = 0x0 (0)
  98. ways of associativity = 0x7 (7)
  99. ways of associativity = 0x0 (0)
  100. WBINVD/INVD behavior on lower caches = false
  101. inclusive to lower caches = false
  102. complex cache indexing = false
  103. number of sets - 1 (s) = 63
  104. --- cache 1 ---
  105. cache type = instruction cache (2)
  106. cache level = 0x1 (1)
  107. self-initializing cache level = true
  108. fully associative cache = false
  109. extra threads sharing this cache = 0x1 (1)
  110. extra processor cores on this die = 0x7 (7)
  111. system coherency line size = 0x3f (63)
  112. physical line partitions = 0x0 (0)
  113. ways of associativity = 0x7 (7)
  114. ways of associativity = 0x0 (0)
  115. WBINVD/INVD behavior on lower caches = false
  116. inclusive to lower caches = false
  117. complex cache indexing = false
  118. number of sets - 1 (s) = 63
  119. --- cache 2 ---
  120. cache type = unified cache (3)
  121. cache level = 0x2 (2)
  122. self-initializing cache level = true
  123. fully associative cache = false
  124. extra threads sharing this cache = 0x1 (1)
  125. extra processor cores on this die = 0x7 (7)
  126. system coherency line size = 0x3f (63)
  127. physical line partitions = 0x0 (0)
  128. ways of associativity = 0x7 (7)
  129. ways of associativity = 0x0 (0)
  130. WBINVD/INVD behavior on lower caches = false
  131. inclusive to lower caches = false
  132. complex cache indexing = false
  133. number of sets - 1 (s) = 511
  134. --- cache 3 ---
  135. cache type = unified cache (3)
  136. cache level = 0x3 (3)
  137. self-initializing cache level = true
  138. fully associative cache = false
  139. extra threads sharing this cache = 0xf (15)
  140. extra processor cores on this die = 0x7 (7)
  141. system coherency line size = 0x3f (63)
  142. physical line partitions = 0x0 (0)
  143. ways of associativity = 0xb (11)
  144. ways of associativity = 0x6 (6)
  145. WBINVD/INVD behavior on lower caches = false
  146. inclusive to lower caches = true
  147. complex cache indexing = true
  148. number of sets - 1 (s) = 4095
  149. MONITOR/MWAIT (5):
  150. smallest monitor-line size (bytes) = 0x40 (64)
  151. largest monitor-line size (bytes) = 0x40 (64)
  152. enum of Monitor-MWAIT exts supported = true
  153. supports intrs as break-event for MWAIT = true
  154. number of C0 sub C-states using MWAIT = 0x0 (0)
  155. number of C1 sub C-states using MWAIT = 0x2 (2)
  156. number of C2 sub C-states using MWAIT = 0x1 (1)
  157. number of C3 sub C-states using MWAIT = 0x2 (2)
  158. number of C4 sub C-states using MWAIT = 0x4 (4)
  159. number of C5 sub C-states using MWAIT = 0x1 (1)
  160. number of C6 sub C-states using MWAIT = 0x1 (1)
  161. number of C7 sub C-states using MWAIT = 0x1 (1)
  162. Thermal and Power Management Features (6):
  163. digital thermometer = true
  164. Intel Turbo Boost Technology = true
  165. ARAT always running APIC timer = true
  166. PLN power limit notification = true
  167. ECMD extended clock modulation duty = true
  168. PTM package thermal management = true
  169. HWP base registers = false
  170. HWP notification = false
  171. HWP activity window = false
  172. HWP energy performance preference = false
  173. HWP package level request = false
  174. HDC base registers = false
  175. digital thermometer thresholds = 0x2 (2)
  176. ACNT/MCNT supported performance measure = true
  177. ACNT2 available = false
  178. performance-energy bias capability = true
  179. extended feature flags (7):
  180. FSGSBASE instructions = true
  181. IA32_TSC_ADJUST MSR supported = true
  182. SGX: Software Guard Extensions supported = false
  183. BMI instruction = true
  184. HLE hardware lock elision = false
  185. AVX2: advanced vector extensions 2 = true
  186. FDP_EXCPTN_ONLY = false
  187. SMEP supervisor mode exec protection = true
  188. BMI2 instructions = true
  189. enhanced REP MOVSB/STOSB = true
  190. INVPCID instruction = true
  191. RTM: restricted transactional memory = false
  192. QM: quality of service monitoring = false
  193. deprecated FPU CS/DS = true
  194. intel memory protection extensions = false
  195. PQE: platform quality of service enforce = false
  196. AVX512F: AVX-512 foundation instructions = false
  197. AVX512DQ: double & quadword instructions = false
  198. RDSEED instruction = false
  199. ADX instructions = false
  200. SMAP: supervisor mode access prevention = false
  201. AVX512IFMA: fused multiply add = false
  202. CLFLUSHOPT instruction = false
  203. CLWB instruction = false
  204. Intel processor trace = false
  205. AVX512PF: prefetch instructions = false
  206. AVX512ER: exponent & reciprocal instrs = false
  207. AVX512CD: conflict detection instrs = false
  208. SHA instructions = false
  209. AVX512BW: byte & word instructions = false
  210. AVX512VL: vector length = false
  211. PREFETCHWT1 = false
  212. AVX512VBMI: vector byte manipulation = false
  213. UMIP: user-mode instruction prevention = false
  214. PKU protection keys for user-mode = false
  215. OSPKE CR4.PKE and RDPKRU/WRPKRU = false
  216. BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
  217. RDPID: read processor D supported = false
  218. SGX_LC: SGX launch config supported = false
  219. AVX512_4VNNIW: neural network instrs = false
  220. AVX512_4FMAPS: multiply acc single prec = false
  221. Direct Cache Access Parameters (9):
  222. PLATFORM_DCA_CAP MSR bits = 0
  223. Architecture Performance Monitoring Features (0xa/eax):
  224. version ID = 0x3 (3)
  225. number of counters per logical processor = 0x4 (4)
  226. bit width of counter = 0x30 (48)
  227. length of EBX bit vector = 0x7 (7)
  228. Architecture Performance Monitoring Features (0xa/ebx):
  229. core cycle event not available = false
  230. instruction retired event not available = false
  231. reference cycles event not available = false
  232. last-level cache ref event not available = false
  233. last-level cache miss event not avail = false
  234. branch inst retired event not available = false
  235. branch mispred retired event not avail = false
  236. Architecture Performance Monitoring Features (0xa/edx):
  237. number of fixed counters = 0x3 (3)
  238. bit width of fixed counters = 0x30 (48)
  239. x2APIC features / processor topology (0xb):
  240. --- level 0 (thread) ---
  241. bits to shift APIC ID to get next = 0x1 (1)
  242. logical processors at this level = 0x2 (2)
  243. level number = 0x0 (0)
  244. level type = thread (1)
  245. extended APIC ID = 0
  246. --- level 1 (core) ---
  247. bits to shift APIC ID to get next = 0x4 (4)
  248. logical processors at this level = 0x4 (4)
  249. level number = 0x1 (1)
  250. level type = core (2)
  251. extended APIC ID = 0
  252. XSAVE features (0xd/0):
  253. XCR0 lower 32 bits valid bit field mask = 0x00000007
  254. XCR0 upper 32 bits valid bit field mask = 0x00000000
  255. XCR0 supported: x87 state = true
  256. XCR0 supported: SSE state = true
  257. XCR0 supported: AVX state = true
  258. XCR0 supported: MPX BNDREGS = false
  259. XCR0 supported: MPX BNDCSR = false
  260. XCR0 supported: AVX-512 opmask = false
  261. XCR0 supported: AVX-512 ZMM_Hi256 = false
  262. XCR0 supported: AVX-512 Hi16_ZMM = false
  263. IA32_XSS supported: PT state = false
  264. XCR0 supported: PKRU state = false
  265. bytes required by fields in XCR0 = 0x00000340 (832)
  266. bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
  267. XSAVE features (0xd/1):
  268. XSAVEOPT instruction = true
  269. XSAVEC instruction = false
  270. XGETBV instruction = false
  271. XSAVES/XRSTORS instructions = false
  272. SAVE area size in bytes = 0x00000000 (0)
  273. IA32_XSS lower 32 bits valid bit field mask = 0x00000000
  274. IA32_XSS upper 32 bits valid bit field mask = 0x00000000
  275. AVX/YMM features (0xd/2):
  276. AVX/YMM save state byte size = 0x00000100 (256)
  277. AVX/YMM save state byte offset = 0x00000240 (576)
  278. supported in IA32_XSS or XCR0 = XCR0 (user state)
  279. 64-byte alignment in compacted XSAVE = false
  280. extended feature flags (0x80000001/edx):
  281. SYSCALL and SYSRET instructions = true
  282. execution disable = true
  283. 1-GB large page support = true
  284. RDTSCP = true
  285. 64-bit extensions technology available = true
  286. Intel feature flags (0x80000001/ecx):
  287. LAHF/SAHF supported in 64-bit mode = true
  288. LZCNT advanced bit manipulation = true
  289. 3DNow! PREFETCH/PREFETCHW instructions = false
  290. brand = "Intel(R) Core(TM) i5-4250U CPU @ 1.30GHz"
  291. L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
  292. instruction # entries = 0x0 (0)
  293. instruction associativity = 0x0 (0)
  294. data # entries = 0x0 (0)
  295. data associativity = 0x0 (0)
  296. L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
  297. instruction # entries = 0x0 (0)
  298. instruction associativity = 0x0 (0)
  299. data # entries = 0x0 (0)
  300. data associativity = 0x0 (0)
  301. L1 data cache information (0x80000005/ecx):
  302. line size (bytes) = 0x0 (0)
  303. lines per tag = 0x0 (0)
  304. associativity = 0x0 (0)
  305. size (KB) = 0x0 (0)
  306. L1 instruction cache information (0x80000005/edx):
  307. line size (bytes) = 0x0 (0)
  308. lines per tag = 0x0 (0)
  309. associativity = 0x0 (0)
  310. size (KB) = 0x0 (0)
  311. L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
  312. instruction # entries = 0x0 (0)
  313. instruction associativity = L2 off (0)
  314. data # entries = 0x0 (0)
  315. data associativity = L2 off (0)
  316. L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
  317. instruction # entries = 0x0 (0)
  318. instruction associativity = L2 off (0)
  319. data # entries = 0x0 (0)
  320. data associativity = L2 off (0)
  321. L2 unified cache information (0x80000006/ecx):
  322. line size (bytes) = 0x40 (64)
  323. lines per tag = 0x0 (0)
  324. associativity = 8-way (6)
  325. size (KB) = 0x100 (256)
  326. L3 cache information (0x80000006/edx):
  327. line size (bytes) = 0x0 (0)
  328. lines per tag = 0x0 (0)
  329. associativity = L2 off (0)
  330. size (in 512KB units) = 0x0 (0)
  331. Advanced Power Management Features (0x80000007/edx):
  332. temperature sensing diode = false
  333. frequency ID (FID) control = false
  334. voltage ID (VID) control = false
  335. thermal trip (TTP) = false
  336. thermal monitor (TM) = false
  337. software thermal control (STC) = false
  338. 100 MHz multiplier control = false
  339. hardware P-State control = false
  340. TscInvariant = true
  341. Physical Address and Linear Address Size (0x80000008/eax):
  342. maximum physical address bits = 0x27 (39)
  343. maximum linear (virtual) address bits = 0x30 (48)
  344. maximum guest physical address bits = 0x0 (0)
  345. Logical CPU cores (0x80000008/ecx):
  346. number of CPU cores - 1 = 0x0 (0)
  347. ApicIdCoreIdSize = 0x0 (0)
  348. (multi-processing synth): multi-core (c=2), hyper-threaded (t=2)
  349. (multi-processing method): Intel leaf 0xb
  350. (APIC widths synth): CORE_width=4 SMT_width=1
  351. (APIC synth): PKG_ID=0 CORE_ID=0 SMT_ID=0
  352. (synth) = Intel Mobile Core i3-4000Y / Mobile Core i5-4000Y / Mobile Core i7-4000Y / Mobile Pentium 3500U/3600U/3500Y / Mobile Celeron 2900U (Mobile U/Y) (Haswell), 22nm
  353. CPU 1:
  354. vendor_id = "GenuineIntel"
  355. version information (1/eax):
  356. processor type = primary processor (0)
  357. family = Intel Pentium Pro/II/III/Celeron/Core/Core 2/Atom, AMD Athlon/Duron, Cyrix M2, VIA C3 (6)
  358. model = 0x5 (5)
  359. stepping id = 0x1 (1)
  360. extended family = 0x0 (0)
  361. extended model = 0x4 (4)
  362. (simple synth) = Intel Mobile Core i3-4000Y / Mobile Core i5-4000Y / Mobile Core i7-4000Y / Mobile Pentium 3500U/3600U/3500Y / Mobile Celeron 2900U (Mobile U/Y) (Haswell), 22nm
  363. miscellaneous (1/ebx):
  364. process local APIC physical ID = 0x2 (2)
  365. cpu count = 0x10 (16)
  366. CLFLUSH line size = 0x8 (8)
  367. brand index = 0x0 (0)
  368. brand id = 0x00 (0): unknown
  369. feature information (1/edx):
  370. x87 FPU on chip = true
  371. virtual-8086 mode enhancement = true
  372. debugging extensions = true
  373. page size extensions = true
  374. time stamp counter = true
  375. RDMSR and WRMSR support = true
  376. physical address extensions = true
  377. machine check exception = true
  378. CMPXCHG8B inst. = true
  379. APIC on chip = true
  380. SYSENTER and SYSEXIT = true
  381. memory type range registers = true
  382. PTE global bit = true
  383. machine check architecture = true
  384. conditional move/compare instruction = true
  385. page attribute table = true
  386. page size extension = true
  387. processor serial number = false
  388. CLFLUSH instruction = true
  389. debug store = true
  390. thermal monitor and clock ctrl = true
  391. MMX Technology = true
  392. FXSAVE/FXRSTOR = true
  393. SSE extensions = true
  394. SSE2 extensions = true
  395. self snoop = true
  396. hyper-threading / multi-core supported = true
  397. therm. monitor = true
  398. IA64 = false
  399. pending break event = true
  400. feature information (1/ecx):
  401. PNI/SSE3: Prescott New Instructions = true
  402. PCLMULDQ instruction = true
  403. 64-bit debug store = true
  404. MONITOR/MWAIT = true
  405. CPL-qualified debug store = true
  406. VMX: virtual machine extensions = true
  407. SMX: safer mode extensions = false
  408. Enhanced Intel SpeedStep Technology = true
  409. thermal monitor 2 = true
  410. SSSE3 extensions = true
  411. context ID: adaptive or shared L1 data = false
  412. FMA instruction = true
  413. CMPXCHG16B instruction = true
  414. xTPR disable = true
  415. perfmon and debug = true
  416. process context identifiers = true
  417. direct cache access = false
  418. SSE4.1 extensions = true
  419. SSE4.2 extensions = true
  420. extended xAPIC support = true
  421. MOVBE instruction = true
  422. POPCNT instruction = true
  423. time stamp counter deadline = true
  424. AES instruction = true
  425. XSAVE/XSTOR states = true
  426. OS-enabled XSAVE/XSTOR = true
  427. AVX: advanced vector extensions = true
  428. F16C half-precision convert instruction = true
  429. RDRAND instruction = true
  430. hypervisor guest status = false
  431. cache and TLB information (2):
  432. 0x63: data TLB: 1G pages, 4-way, 4 entries
  433. 0x03: data TLB: 4K pages, 4-way, 64 entries
  434. 0x76: instruction TLB: 2M/4M pages, fully, 8 entries
  435. 0xff: cache data is in CPUID 4
  436. 0xb5: instruction TLB: 4K, 8-way, 64 entries
  437. 0xf0: 64 byte prefetching
  438. 0xc1: L2 TLB: 4K/2M pages, 8-way, 1024 entries
  439. processor serial number: 0004-0651-0000-0000-0000-0000
  440. deterministic cache parameters (4):
  441. --- cache 0 ---
  442. cache type = data cache (1)
  443. cache level = 0x1 (1)
  444. self-initializing cache level = true
  445. fully associative cache = false
  446. extra threads sharing this cache = 0x1 (1)
  447. extra processor cores on this die = 0x7 (7)
  448. system coherency line size = 0x3f (63)
  449. physical line partitions = 0x0 (0)
  450. ways of associativity = 0x7 (7)
  451. ways of associativity = 0x0 (0)
  452. WBINVD/INVD behavior on lower caches = false
  453. inclusive to lower caches = false
  454. complex cache indexing = false
  455. number of sets - 1 (s) = 63
  456. --- cache 1 ---
  457. cache type = instruction cache (2)
  458. cache level = 0x1 (1)
  459. self-initializing cache level = true
  460. fully associative cache = false
  461. extra threads sharing this cache = 0x1 (1)
  462. extra processor cores on this die = 0x7 (7)
  463. system coherency line size = 0x3f (63)
  464. physical line partitions = 0x0 (0)
  465. ways of associativity = 0x7 (7)
  466. ways of associativity = 0x0 (0)
  467. WBINVD/INVD behavior on lower caches = false
  468. inclusive to lower caches = false
  469. complex cache indexing = false
  470. number of sets - 1 (s) = 63
  471. --- cache 2 ---
  472. cache type = unified cache (3)
  473. cache level = 0x2 (2)
  474. self-initializing cache level = true
  475. fully associative cache = false
  476. extra threads sharing this cache = 0x1 (1)
  477. extra processor cores on this die = 0x7 (7)
  478. system coherency line size = 0x3f (63)
  479. physical line partitions = 0x0 (0)
  480. ways of associativity = 0x7 (7)
  481. ways of associativity = 0x0 (0)
  482. WBINVD/INVD behavior on lower caches = false
  483. inclusive to lower caches = false
  484. complex cache indexing = false
  485. number of sets - 1 (s) = 511
  486. --- cache 3 ---
  487. cache type = unified cache (3)
  488. cache level = 0x3 (3)
  489. self-initializing cache level = true
  490. fully associative cache = false
  491. extra threads sharing this cache = 0xf (15)
  492. extra processor cores on this die = 0x7 (7)
  493. system coherency line size = 0x3f (63)
  494. physical line partitions = 0x0 (0)
  495. ways of associativity = 0xb (11)
  496. ways of associativity = 0x6 (6)
  497. WBINVD/INVD behavior on lower caches = false
  498. inclusive to lower caches = true
  499. complex cache indexing = true
  500. number of sets - 1 (s) = 4095
  501. MONITOR/MWAIT (5):
  502. smallest monitor-line size (bytes) = 0x40 (64)
  503. largest monitor-line size (bytes) = 0x40 (64)
  504. enum of Monitor-MWAIT exts supported = true
  505. supports intrs as break-event for MWAIT = true
  506. number of C0 sub C-states using MWAIT = 0x0 (0)
  507. number of C1 sub C-states using MWAIT = 0x2 (2)
  508. number of C2 sub C-states using MWAIT = 0x1 (1)
  509. number of C3 sub C-states using MWAIT = 0x2 (2)
  510. number of C4 sub C-states using MWAIT = 0x4 (4)
  511. number of C5 sub C-states using MWAIT = 0x1 (1)
  512. number of C6 sub C-states using MWAIT = 0x1 (1)
  513. number of C7 sub C-states using MWAIT = 0x1 (1)
  514. Thermal and Power Management Features (6):
  515. digital thermometer = true
  516. Intel Turbo Boost Technology = true
  517. ARAT always running APIC timer = true
  518. PLN power limit notification = true
  519. ECMD extended clock modulation duty = true
  520. PTM package thermal management = true
  521. HWP base registers = false
  522. HWP notification = false
  523. HWP activity window = false
  524. HWP energy performance preference = false
  525. HWP package level request = false
  526. HDC base registers = false
  527. digital thermometer thresholds = 0x2 (2)
  528. ACNT/MCNT supported performance measure = true
  529. ACNT2 available = false
  530. performance-energy bias capability = true
  531. extended feature flags (7):
  532. FSGSBASE instructions = true
  533. IA32_TSC_ADJUST MSR supported = true
  534. SGX: Software Guard Extensions supported = false
  535. BMI instruction = true
  536. HLE hardware lock elision = false
  537. AVX2: advanced vector extensions 2 = true
  538. FDP_EXCPTN_ONLY = false
  539. SMEP supervisor mode exec protection = true
  540. BMI2 instructions = true
  541. enhanced REP MOVSB/STOSB = true
  542. INVPCID instruction = true
  543. RTM: restricted transactional memory = false
  544. QM: quality of service monitoring = false
  545. deprecated FPU CS/DS = true
  546. intel memory protection extensions = false
  547. PQE: platform quality of service enforce = false
  548. AVX512F: AVX-512 foundation instructions = false
  549. AVX512DQ: double & quadword instructions = false
  550. RDSEED instruction = false
  551. ADX instructions = false
  552. SMAP: supervisor mode access prevention = false
  553. AVX512IFMA: fused multiply add = false
  554. CLFLUSHOPT instruction = false
  555. CLWB instruction = false
  556. Intel processor trace = false
  557. AVX512PF: prefetch instructions = false
  558. AVX512ER: exponent & reciprocal instrs = false
  559. AVX512CD: conflict detection instrs = false
  560. SHA instructions = false
  561. AVX512BW: byte & word instructions = false
  562. AVX512VL: vector length = false
  563. PREFETCHWT1 = false
  564. AVX512VBMI: vector byte manipulation = false
  565. UMIP: user-mode instruction prevention = false
  566. PKU protection keys for user-mode = false
  567. OSPKE CR4.PKE and RDPKRU/WRPKRU = false
  568. BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
  569. RDPID: read processor D supported = false
  570. SGX_LC: SGX launch config supported = false
  571. AVX512_4VNNIW: neural network instrs = false
  572. AVX512_4FMAPS: multiply acc single prec = false
  573. Direct Cache Access Parameters (9):
  574. PLATFORM_DCA_CAP MSR bits = 0
  575. Architecture Performance Monitoring Features (0xa/eax):
  576. version ID = 0x3 (3)
  577. number of counters per logical processor = 0x4 (4)
  578. bit width of counter = 0x30 (48)
  579. length of EBX bit vector = 0x7 (7)
  580. Architecture Performance Monitoring Features (0xa/ebx):
  581. core cycle event not available = false
  582. instruction retired event not available = false
  583. reference cycles event not available = false
  584. last-level cache ref event not available = false
  585. last-level cache miss event not avail = false
  586. branch inst retired event not available = false
  587. branch mispred retired event not avail = false
  588. Architecture Performance Monitoring Features (0xa/edx):
  589. number of fixed counters = 0x3 (3)
  590. bit width of fixed counters = 0x30 (48)
  591. x2APIC features / processor topology (0xb):
  592. --- level 0 (thread) ---
  593. bits to shift APIC ID to get next = 0x1 (1)
  594. logical processors at this level = 0x2 (2)
  595. level number = 0x0 (0)
  596. level type = thread (1)
  597. extended APIC ID = 2
  598. --- level 1 (core) ---
  599. bits to shift APIC ID to get next = 0x4 (4)
  600. logical processors at this level = 0x4 (4)
  601. level number = 0x1 (1)
  602. level type = core (2)
  603. extended APIC ID = 2
  604. XSAVE features (0xd/0):
  605. XCR0 lower 32 bits valid bit field mask = 0x00000007
  606. XCR0 upper 32 bits valid bit field mask = 0x00000000
  607. XCR0 supported: x87 state = true
  608. XCR0 supported: SSE state = true
  609. XCR0 supported: AVX state = true
  610. XCR0 supported: MPX BNDREGS = false
  611. XCR0 supported: MPX BNDCSR = false
  612. XCR0 supported: AVX-512 opmask = false
  613. XCR0 supported: AVX-512 ZMM_Hi256 = false
  614. XCR0 supported: AVX-512 Hi16_ZMM = false
  615. IA32_XSS supported: PT state = false
  616. XCR0 supported: PKRU state = false
  617. bytes required by fields in XCR0 = 0x00000340 (832)
  618. bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
  619. XSAVE features (0xd/1):
  620. XSAVEOPT instruction = true
  621. XSAVEC instruction = false
  622. XGETBV instruction = false
  623. XSAVES/XRSTORS instructions = false
  624. SAVE area size in bytes = 0x00000000 (0)
  625. IA32_XSS lower 32 bits valid bit field mask = 0x00000000
  626. IA32_XSS upper 32 bits valid bit field mask = 0x00000000
  627. AVX/YMM features (0xd/2):
  628. AVX/YMM save state byte size = 0x00000100 (256)
  629. AVX/YMM save state byte offset = 0x00000240 (576)
  630. supported in IA32_XSS or XCR0 = XCR0 (user state)
  631. 64-byte alignment in compacted XSAVE = false
  632. extended feature flags (0x80000001/edx):
  633. SYSCALL and SYSRET instructions = true
  634. execution disable = true
  635. 1-GB large page support = true
  636. RDTSCP = true
  637. 64-bit extensions technology available = true
  638. Intel feature flags (0x80000001/ecx):
  639. LAHF/SAHF supported in 64-bit mode = true
  640. LZCNT advanced bit manipulation = true
  641. 3DNow! PREFETCH/PREFETCHW instructions = false
  642. brand = "Intel(R) Core(TM) i5-4250U CPU @ 1.30GHz"
  643. L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
  644. instruction # entries = 0x0 (0)
  645. instruction associativity = 0x0 (0)
  646. data # entries = 0x0 (0)
  647. data associativity = 0x0 (0)
  648. L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
  649. instruction # entries = 0x0 (0)
  650. instruction associativity = 0x0 (0)
  651. data # entries = 0x0 (0)
  652. data associativity = 0x0 (0)
  653. L1 data cache information (0x80000005/ecx):
  654. line size (bytes) = 0x0 (0)
  655. lines per tag = 0x0 (0)
  656. associativity = 0x0 (0)
  657. size (KB) = 0x0 (0)
  658. L1 instruction cache information (0x80000005/edx):
  659. line size (bytes) = 0x0 (0)
  660. lines per tag = 0x0 (0)
  661. associativity = 0x0 (0)
  662. size (KB) = 0x0 (0)
  663. L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
  664. instruction # entries = 0x0 (0)
  665. instruction associativity = L2 off (0)
  666. data # entries = 0x0 (0)
  667. data associativity = L2 off (0)
  668. L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
  669. instruction # entries = 0x0 (0)
  670. instruction associativity = L2 off (0)
  671. data # entries = 0x0 (0)
  672. data associativity = L2 off (0)
  673. L2 unified cache information (0x80000006/ecx):
  674. line size (bytes) = 0x40 (64)
  675. lines per tag = 0x0 (0)
  676. associativity = 8-way (6)
  677. size (KB) = 0x100 (256)
  678. L3 cache information (0x80000006/edx):
  679. line size (bytes) = 0x0 (0)
  680. lines per tag = 0x0 (0)
  681. associativity = L2 off (0)
  682. size (in 512KB units) = 0x0 (0)
  683. Advanced Power Management Features (0x80000007/edx):
  684. temperature sensing diode = false
  685. frequency ID (FID) control = false
  686. voltage ID (VID) control = false
  687. thermal trip (TTP) = false
  688. thermal monitor (TM) = false
  689. software thermal control (STC) = false
  690. 100 MHz multiplier control = false
  691. hardware P-State control = false
  692. TscInvariant = true
  693. Physical Address and Linear Address Size (0x80000008/eax):
  694. maximum physical address bits = 0x27 (39)
  695. maximum linear (virtual) address bits = 0x30 (48)
  696. maximum guest physical address bits = 0x0 (0)
  697. Logical CPU cores (0x80000008/ecx):
  698. number of CPU cores - 1 = 0x0 (0)
  699. ApicIdCoreIdSize = 0x0 (0)
  700. (multi-processing synth): multi-core (c=2), hyper-threaded (t=2)
  701. (multi-processing method): Intel leaf 0xb
  702. (APIC widths synth): CORE_width=4 SMT_width=1
  703. (APIC synth): PKG_ID=0 CORE_ID=1 SMT_ID=0
  704. (synth) = Intel Mobile Core i3-4000Y / Mobile Core i5-4000Y / Mobile Core i7-4000Y / Mobile Pentium 3500U/3600U/3500Y / Mobile Celeron 2900U (Mobile U/Y) (Haswell), 22nm
  705. CPU 2:
  706. vendor_id = "GenuineIntel"
  707. version information (1/eax):
  708. processor type = primary processor (0)
  709. family = Intel Pentium Pro/II/III/Celeron/Core/Core 2/Atom, AMD Athlon/Duron, Cyrix M2, VIA C3 (6)
  710. model = 0x5 (5)
  711. stepping id = 0x1 (1)
  712. extended family = 0x0 (0)
  713. extended model = 0x4 (4)
  714. (simple synth) = Intel Mobile Core i3-4000Y / Mobile Core i5-4000Y / Mobile Core i7-4000Y / Mobile Pentium 3500U/3600U/3500Y / Mobile Celeron 2900U (Mobile U/Y) (Haswell), 22nm
  715. miscellaneous (1/ebx):
  716. process local APIC physical ID = 0x1 (1)
  717. cpu count = 0x10 (16)
  718. CLFLUSH line size = 0x8 (8)
  719. brand index = 0x0 (0)
  720. brand id = 0x00 (0): unknown
  721. feature information (1/edx):
  722. x87 FPU on chip = true
  723. virtual-8086 mode enhancement = true
  724. debugging extensions = true
  725. page size extensions = true
  726. time stamp counter = true
  727. RDMSR and WRMSR support = true
  728. physical address extensions = true
  729. machine check exception = true
  730. CMPXCHG8B inst. = true
  731. APIC on chip = true
  732. SYSENTER and SYSEXIT = true
  733. memory type range registers = true
  734. PTE global bit = true
  735. machine check architecture = true
  736. conditional move/compare instruction = true
  737. page attribute table = true
  738. page size extension = true
  739. processor serial number = false
  740. CLFLUSH instruction = true
  741. debug store = true
  742. thermal monitor and clock ctrl = true
  743. MMX Technology = true
  744. FXSAVE/FXRSTOR = true
  745. SSE extensions = true
  746. SSE2 extensions = true
  747. self snoop = true
  748. hyper-threading / multi-core supported = true
  749. therm. monitor = true
  750. IA64 = false
  751. pending break event = true
  752. feature information (1/ecx):
  753. PNI/SSE3: Prescott New Instructions = true
  754. PCLMULDQ instruction = true
  755. 64-bit debug store = true
  756. MONITOR/MWAIT = true
  757. CPL-qualified debug store = true
  758. VMX: virtual machine extensions = true
  759. SMX: safer mode extensions = false
  760. Enhanced Intel SpeedStep Technology = true
  761. thermal monitor 2 = true
  762. SSSE3 extensions = true
  763. context ID: adaptive or shared L1 data = false
  764. FMA instruction = true
  765. CMPXCHG16B instruction = true
  766. xTPR disable = true
  767. perfmon and debug = true
  768. process context identifiers = true
  769. direct cache access = false
  770. SSE4.1 extensions = true
  771. SSE4.2 extensions = true
  772. extended xAPIC support = true
  773. MOVBE instruction = true
  774. POPCNT instruction = true
  775. time stamp counter deadline = true
  776. AES instruction = true
  777. XSAVE/XSTOR states = true
  778. OS-enabled XSAVE/XSTOR = true
  779. AVX: advanced vector extensions = true
  780. F16C half-precision convert instruction = true
  781. RDRAND instruction = true
  782. hypervisor guest status = false
  783. cache and TLB information (2):
  784. 0x63: data TLB: 1G pages, 4-way, 4 entries
  785. 0x03: data TLB: 4K pages, 4-way, 64 entries
  786. 0x76: instruction TLB: 2M/4M pages, fully, 8 entries
  787. 0xff: cache data is in CPUID 4
  788. 0xb5: instruction TLB: 4K, 8-way, 64 entries
  789. 0xf0: 64 byte prefetching
  790. 0xc1: L2 TLB: 4K/2M pages, 8-way, 1024 entries
  791. processor serial number: 0004-0651-0000-0000-0000-0000
  792. deterministic cache parameters (4):
  793. --- cache 0 ---
  794. cache type = data cache (1)
  795. cache level = 0x1 (1)
  796. self-initializing cache level = true
  797. fully associative cache = false
  798. extra threads sharing this cache = 0x1 (1)
  799. extra processor cores on this die = 0x7 (7)
  800. system coherency line size = 0x3f (63)
  801. physical line partitions = 0x0 (0)
  802. ways of associativity = 0x7 (7)
  803. ways of associativity = 0x0 (0)
  804. WBINVD/INVD behavior on lower caches = false
  805. inclusive to lower caches = false
  806. complex cache indexing = false
  807. number of sets - 1 (s) = 63
  808. --- cache 1 ---
  809. cache type = instruction cache (2)
  810. cache level = 0x1 (1)
  811. self-initializing cache level = true
  812. fully associative cache = false
  813. extra threads sharing this cache = 0x1 (1)
  814. extra processor cores on this die = 0x7 (7)
  815. system coherency line size = 0x3f (63)
  816. physical line partitions = 0x0 (0)
  817. ways of associativity = 0x7 (7)
  818. ways of associativity = 0x0 (0)
  819. WBINVD/INVD behavior on lower caches = false
  820. inclusive to lower caches = false
  821. complex cache indexing = false
  822. number of sets - 1 (s) = 63
  823. --- cache 2 ---
  824. cache type = unified cache (3)
  825. cache level = 0x2 (2)
  826. self-initializing cache level = true
  827. fully associative cache = false
  828. extra threads sharing this cache = 0x1 (1)
  829. extra processor cores on this die = 0x7 (7)
  830. system coherency line size = 0x3f (63)
  831. physical line partitions = 0x0 (0)
  832. ways of associativity = 0x7 (7)
  833. ways of associativity = 0x0 (0)
  834. WBINVD/INVD behavior on lower caches = false
  835. inclusive to lower caches = false
  836. complex cache indexing = false
  837. number of sets - 1 (s) = 511
  838. --- cache 3 ---
  839. cache type = unified cache (3)
  840. cache level = 0x3 (3)
  841. self-initializing cache level = true
  842. fully associative cache = false
  843. extra threads sharing this cache = 0xf (15)
  844. extra processor cores on this die = 0x7 (7)
  845. system coherency line size = 0x3f (63)
  846. physical line partitions = 0x0 (0)
  847. ways of associativity = 0xb (11)
  848. ways of associativity = 0x6 (6)
  849. WBINVD/INVD behavior on lower caches = false
  850. inclusive to lower caches = true
  851. complex cache indexing = true
  852. number of sets - 1 (s) = 4095
  853. MONITOR/MWAIT (5):
  854. smallest monitor-line size (bytes) = 0x40 (64)
  855. largest monitor-line size (bytes) = 0x40 (64)
  856. enum of Monitor-MWAIT exts supported = true
  857. supports intrs as break-event for MWAIT = true
  858. number of C0 sub C-states using MWAIT = 0x0 (0)
  859. number of C1 sub C-states using MWAIT = 0x2 (2)
  860. number of C2 sub C-states using MWAIT = 0x1 (1)
  861. number of C3 sub C-states using MWAIT = 0x2 (2)
  862. number of C4 sub C-states using MWAIT = 0x4 (4)
  863. number of C5 sub C-states using MWAIT = 0x1 (1)
  864. number of C6 sub C-states using MWAIT = 0x1 (1)
  865. number of C7 sub C-states using MWAIT = 0x1 (1)
  866. Thermal and Power Management Features (6):
  867. digital thermometer = true
  868. Intel Turbo Boost Technology = true
  869. ARAT always running APIC timer = true
  870. PLN power limit notification = true
  871. ECMD extended clock modulation duty = true
  872. PTM package thermal management = true
  873. HWP base registers = false
  874. HWP notification = false
  875. HWP activity window = false
  876. HWP energy performance preference = false
  877. HWP package level request = false
  878. HDC base registers = false
  879. digital thermometer thresholds = 0x2 (2)
  880. ACNT/MCNT supported performance measure = true
  881. ACNT2 available = false
  882. performance-energy bias capability = true
  883. extended feature flags (7):
  884. FSGSBASE instructions = true
  885. IA32_TSC_ADJUST MSR supported = true
  886. SGX: Software Guard Extensions supported = false
  887. BMI instruction = true
  888. HLE hardware lock elision = false
  889. AVX2: advanced vector extensions 2 = true
  890. FDP_EXCPTN_ONLY = false
  891. SMEP supervisor mode exec protection = true
  892. BMI2 instructions = true
  893. enhanced REP MOVSB/STOSB = true
  894. INVPCID instruction = true
  895. RTM: restricted transactional memory = false
  896. QM: quality of service monitoring = false
  897. deprecated FPU CS/DS = true
  898. intel memory protection extensions = false
  899. PQE: platform quality of service enforce = false
  900. AVX512F: AVX-512 foundation instructions = false
  901. AVX512DQ: double & quadword instructions = false
  902. RDSEED instruction = false
  903. ADX instructions = false
  904. SMAP: supervisor mode access prevention = false
  905. AVX512IFMA: fused multiply add = false
  906. CLFLUSHOPT instruction = false
  907. CLWB instruction = false
  908. Intel processor trace = false
  909. AVX512PF: prefetch instructions = false
  910. AVX512ER: exponent & reciprocal instrs = false
  911. AVX512CD: conflict detection instrs = false
  912. SHA instructions = false
  913. AVX512BW: byte & word instructions = false
  914. AVX512VL: vector length = false
  915. PREFETCHWT1 = false
  916. AVX512VBMI: vector byte manipulation = false
  917. UMIP: user-mode instruction prevention = false
  918. PKU protection keys for user-mode = false
  919. OSPKE CR4.PKE and RDPKRU/WRPKRU = false
  920. BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
  921. RDPID: read processor D supported = false
  922. SGX_LC: SGX launch config supported = false
  923. AVX512_4VNNIW: neural network instrs = false
  924. AVX512_4FMAPS: multiply acc single prec = false
  925. Direct Cache Access Parameters (9):
  926. PLATFORM_DCA_CAP MSR bits = 0
  927. Architecture Performance Monitoring Features (0xa/eax):
  928. version ID = 0x3 (3)
  929. number of counters per logical processor = 0x4 (4)
  930. bit width of counter = 0x30 (48)
  931. length of EBX bit vector = 0x7 (7)
  932. Architecture Performance Monitoring Features (0xa/ebx):
  933. core cycle event not available = false
  934. instruction retired event not available = false
  935. reference cycles event not available = false
  936. last-level cache ref event not available = false
  937. last-level cache miss event not avail = false
  938. branch inst retired event not available = false
  939. branch mispred retired event not avail = false
  940. Architecture Performance Monitoring Features (0xa/edx):
  941. number of fixed counters = 0x3 (3)
  942. bit width of fixed counters = 0x30 (48)
  943. x2APIC features / processor topology (0xb):
  944. --- level 0 (thread) ---
  945. bits to shift APIC ID to get next = 0x1 (1)
  946. logical processors at this level = 0x2 (2)
  947. level number = 0x0 (0)
  948. level type = thread (1)
  949. extended APIC ID = 1
  950. --- level 1 (core) ---
  951. bits to shift APIC ID to get next = 0x4 (4)
  952. logical processors at this level = 0x4 (4)
  953. level number = 0x1 (1)
  954. level type = core (2)
  955. extended APIC ID = 1
  956. XSAVE features (0xd/0):
  957. XCR0 lower 32 bits valid bit field mask = 0x00000007
  958. XCR0 upper 32 bits valid bit field mask = 0x00000000
  959. XCR0 supported: x87 state = true
  960. XCR0 supported: SSE state = true
  961. XCR0 supported: AVX state = true
  962. XCR0 supported: MPX BNDREGS = false
  963. XCR0 supported: MPX BNDCSR = false
  964. XCR0 supported: AVX-512 opmask = false
  965. XCR0 supported: AVX-512 ZMM_Hi256 = false
  966. XCR0 supported: AVX-512 Hi16_ZMM = false
  967. IA32_XSS supported: PT state = false
  968. XCR0 supported: PKRU state = false
  969. bytes required by fields in XCR0 = 0x00000340 (832)
  970. bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
  971. XSAVE features (0xd/1):
  972. XSAVEOPT instruction = true
  973. XSAVEC instruction = false
  974. XGETBV instruction = false
  975. XSAVES/XRSTORS instructions = false
  976. SAVE area size in bytes = 0x00000000 (0)
  977. IA32_XSS lower 32 bits valid bit field mask = 0x00000000
  978. IA32_XSS upper 32 bits valid bit field mask = 0x00000000
  979. AVX/YMM features (0xd/2):
  980. AVX/YMM save state byte size = 0x00000100 (256)
  981. AVX/YMM save state byte offset = 0x00000240 (576)
  982. supported in IA32_XSS or XCR0 = XCR0 (user state)
  983. 64-byte alignment in compacted XSAVE = false
  984. extended feature flags (0x80000001/edx):
  985. SYSCALL and SYSRET instructions = true
  986. execution disable = true
  987. 1-GB large page support = true
  988. RDTSCP = true
  989. 64-bit extensions technology available = true
  990. Intel feature flags (0x80000001/ecx):
  991. LAHF/SAHF supported in 64-bit mode = true
  992. LZCNT advanced bit manipulation = true
  993. 3DNow! PREFETCH/PREFETCHW instructions = false
  994. brand = "Intel(R) Core(TM) i5-4250U CPU @ 1.30GHz"
  995. L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
  996. instruction # entries = 0x0 (0)
  997. instruction associativity = 0x0 (0)
  998. data # entries = 0x0 (0)
  999. data associativity = 0x0 (0)
  1000. L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
  1001. instruction # entries = 0x0 (0)
  1002. instruction associativity = 0x0 (0)
  1003. data # entries = 0x0 (0)
  1004. data associativity = 0x0 (0)
  1005. L1 data cache information (0x80000005/ecx):
  1006. line size (bytes) = 0x0 (0)
  1007. lines per tag = 0x0 (0)
  1008. associativity = 0x0 (0)
  1009. size (KB) = 0x0 (0)
  1010. L1 instruction cache information (0x80000005/edx):
  1011. line size (bytes) = 0x0 (0)
  1012. lines per tag = 0x0 (0)
  1013. associativity = 0x0 (0)
  1014. size (KB) = 0x0 (0)
  1015. L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
  1016. instruction # entries = 0x0 (0)
  1017. instruction associativity = L2 off (0)
  1018. data # entries = 0x0 (0)
  1019. data associativity = L2 off (0)
  1020. L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
  1021. instruction # entries = 0x0 (0)
  1022. instruction associativity = L2 off (0)
  1023. data # entries = 0x0 (0)
  1024. data associativity = L2 off (0)
  1025. L2 unified cache information (0x80000006/ecx):
  1026. line size (bytes) = 0x40 (64)
  1027. lines per tag = 0x0 (0)
  1028. associativity = 8-way (6)
  1029. size (KB) = 0x100 (256)
  1030. L3 cache information (0x80000006/edx):
  1031. line size (bytes) = 0x0 (0)
  1032. lines per tag = 0x0 (0)
  1033. associativity = L2 off (0)
  1034. size (in 512KB units) = 0x0 (0)
  1035. Advanced Power Management Features (0x80000007/edx):
  1036. temperature sensing diode = false
  1037. frequency ID (FID) control = false
  1038. voltage ID (VID) control = false
  1039. thermal trip (TTP) = false
  1040. thermal monitor (TM) = false
  1041. software thermal control (STC) = false
  1042. 100 MHz multiplier control = false
  1043. hardware P-State control = false
  1044. TscInvariant = true
  1045. Physical Address and Linear Address Size (0x80000008/eax):
  1046. maximum physical address bits = 0x27 (39)
  1047. maximum linear (virtual) address bits = 0x30 (48)
  1048. maximum guest physical address bits = 0x0 (0)
  1049. Logical CPU cores (0x80000008/ecx):
  1050. number of CPU cores - 1 = 0x0 (0)
  1051. ApicIdCoreIdSize = 0x0 (0)
  1052. (multi-processing synth): multi-core (c=2), hyper-threaded (t=2)
  1053. (multi-processing method): Intel leaf 0xb
  1054. (APIC widths synth): CORE_width=4 SMT_width=1
  1055. (APIC synth): PKG_ID=0 CORE_ID=0 SMT_ID=1
  1056. (synth) = Intel Mobile Core i3-4000Y / Mobile Core i5-4000Y / Mobile Core i7-4000Y / Mobile Pentium 3500U/3600U/3500Y / Mobile Celeron 2900U (Mobile U/Y) (Haswell), 22nm
  1057. CPU 3:
  1058. vendor_id = "GenuineIntel"
  1059. version information (1/eax):
  1060. processor type = primary processor (0)
  1061. family = Intel Pentium Pro/II/III/Celeron/Core/Core 2/Atom, AMD Athlon/Duron, Cyrix M2, VIA C3 (6)
  1062. model = 0x5 (5)
  1063. stepping id = 0x1 (1)
  1064. extended family = 0x0 (0)
  1065. extended model = 0x4 (4)
  1066. (simple synth) = Intel Mobile Core i3-4000Y / Mobile Core i5-4000Y / Mobile Core i7-4000Y / Mobile Pentium 3500U/3600U/3500Y / Mobile Celeron 2900U (Mobile U/Y) (Haswell), 22nm
  1067. miscellaneous (1/ebx):
  1068. process local APIC physical ID = 0x3 (3)
  1069. cpu count = 0x10 (16)
  1070. CLFLUSH line size = 0x8 (8)
  1071. brand index = 0x0 (0)
  1072. brand id = 0x00 (0): unknown
  1073. feature information (1/edx):
  1074. x87 FPU on chip = true
  1075. virtual-8086 mode enhancement = true
  1076. debugging extensions = true
  1077. page size extensions = true
  1078. time stamp counter = true
  1079. RDMSR and WRMSR support = true
  1080. physical address extensions = true
  1081. machine check exception = true
  1082. CMPXCHG8B inst. = true
  1083. APIC on chip = true
  1084. SYSENTER and SYSEXIT = true
  1085. memory type range registers = true
  1086. PTE global bit = true
  1087. machine check architecture = true
  1088. conditional move/compare instruction = true
  1089. page attribute table = true
  1090. page size extension = true
  1091. processor serial number = false
  1092. CLFLUSH instruction = true
  1093. debug store = true
  1094. thermal monitor and clock ctrl = true
  1095. MMX Technology = true
  1096. FXSAVE/FXRSTOR = true
  1097. SSE extensions = true
  1098. SSE2 extensions = true
  1099. self snoop = true
  1100. hyper-threading / multi-core supported = true
  1101. therm. monitor = true
  1102. IA64 = false
  1103. pending break event = true
  1104. feature information (1/ecx):
  1105. PNI/SSE3: Prescott New Instructions = true
  1106. PCLMULDQ instruction = true
  1107. 64-bit debug store = true
  1108. MONITOR/MWAIT = true
  1109. CPL-qualified debug store = true
  1110. VMX: virtual machine extensions = true
  1111. SMX: safer mode extensions = false
  1112. Enhanced Intel SpeedStep Technology = true
  1113. thermal monitor 2 = true
  1114. SSSE3 extensions = true
  1115. context ID: adaptive or shared L1 data = false
  1116. FMA instruction = true
  1117. CMPXCHG16B instruction = true
  1118. xTPR disable = true
  1119. perfmon and debug = true
  1120. process context identifiers = true
  1121. direct cache access = false
  1122. SSE4.1 extensions = true
  1123. SSE4.2 extensions = true
  1124. extended xAPIC support = true
  1125. MOVBE instruction = true
  1126. POPCNT instruction = true
  1127. time stamp counter deadline = true
  1128. AES instruction = true
  1129. XSAVE/XSTOR states = true
  1130. OS-enabled XSAVE/XSTOR = true
  1131. AVX: advanced vector extensions = true
  1132. F16C half-precision convert instruction = true
  1133. RDRAND instruction = true
  1134. hypervisor guest status = false
  1135. cache and TLB information (2):
  1136. 0x63: data TLB: 1G pages, 4-way, 4 entries
  1137. 0x03: data TLB: 4K pages, 4-way, 64 entries
  1138. 0x76: instruction TLB: 2M/4M pages, fully, 8 entries
  1139. 0xff: cache data is in CPUID 4
  1140. 0xb5: instruction TLB: 4K, 8-way, 64 entries
  1141. 0xf0: 64 byte prefetching
  1142. 0xc1: L2 TLB: 4K/2M pages, 8-way, 1024 entries
  1143. processor serial number: 0004-0651-0000-0000-0000-0000
  1144. deterministic cache parameters (4):
  1145. --- cache 0 ---
  1146. cache type = data cache (1)
  1147. cache level = 0x1 (1)
  1148. self-initializing cache level = true
  1149. fully associative cache = false
  1150. extra threads sharing this cache = 0x1 (1)
  1151. extra processor cores on this die = 0x7 (7)
  1152. system coherency line size = 0x3f (63)
  1153. physical line partitions = 0x0 (0)
  1154. ways of associativity = 0x7 (7)
  1155. ways of associativity = 0x0 (0)
  1156. WBINVD/INVD behavior on lower caches = false
  1157. inclusive to lower caches = false
  1158. complex cache indexing = false
  1159. number of sets - 1 (s) = 63
  1160. --- cache 1 ---
  1161. cache type = instruction cache (2)
  1162. cache level = 0x1 (1)
  1163. self-initializing cache level = true
  1164. fully associative cache = false
  1165. extra threads sharing this cache = 0x1 (1)
  1166. extra processor cores on this die = 0x7 (7)
  1167. system coherency line size = 0x3f (63)
  1168. physical line partitions = 0x0 (0)
  1169. ways of associativity = 0x7 (7)
  1170. ways of associativity = 0x0 (0)
  1171. WBINVD/INVD behavior on lower caches = false
  1172. inclusive to lower caches = false
  1173. complex cache indexing = false
  1174. number of sets - 1 (s) = 63
  1175. --- cache 2 ---
  1176. cache type = unified cache (3)
  1177. cache level = 0x2 (2)
  1178. self-initializing cache level = true
  1179. fully associative cache = false
  1180. extra threads sharing this cache = 0x1 (1)
  1181. extra processor cores on this die = 0x7 (7)
  1182. system coherency line size = 0x3f (63)
  1183. physical line partitions = 0x0 (0)
  1184. ways of associativity = 0x7 (7)
  1185. ways of associativity = 0x0 (0)
  1186. WBINVD/INVD behavior on lower caches = false
  1187. inclusive to lower caches = false
  1188. complex cache indexing = false
  1189. number of sets - 1 (s) = 511
  1190. --- cache 3 ---
  1191. cache type = unified cache (3)
  1192. cache level = 0x3 (3)
  1193. self-initializing cache level = true
  1194. fully associative cache = false
  1195. extra threads sharing this cache = 0xf (15)
  1196. extra processor cores on this die = 0x7 (7)
  1197. system coherency line size = 0x3f (63)
  1198. physical line partitions = 0x0 (0)
  1199. ways of associativity = 0xb (11)
  1200. ways of associativity = 0x6 (6)
  1201. WBINVD/INVD behavior on lower caches = false
  1202. inclusive to lower caches = true
  1203. complex cache indexing = true
  1204. number of sets - 1 (s) = 4095
  1205. MONITOR/MWAIT (5):
  1206. smallest monitor-line size (bytes) = 0x40 (64)
  1207. largest monitor-line size (bytes) = 0x40 (64)
  1208. enum of Monitor-MWAIT exts supported = true
  1209. supports intrs as break-event for MWAIT = true
  1210. number of C0 sub C-states using MWAIT = 0x0 (0)
  1211. number of C1 sub C-states using MWAIT = 0x2 (2)
  1212. number of C2 sub C-states using MWAIT = 0x1 (1)
  1213. number of C3 sub C-states using MWAIT = 0x2 (2)
  1214. number of C4 sub C-states using MWAIT = 0x4 (4)
  1215. number of C5 sub C-states using MWAIT = 0x1 (1)
  1216. number of C6 sub C-states using MWAIT = 0x1 (1)
  1217. number of C7 sub C-states using MWAIT = 0x1 (1)
  1218. Thermal and Power Management Features (6):
  1219. digital thermometer = true
  1220. Intel Turbo Boost Technology = true
  1221. ARAT always running APIC timer = true
  1222. PLN power limit notification = true
  1223. ECMD extended clock modulation duty = true
  1224. PTM package thermal management = true
  1225. HWP base registers = false
  1226. HWP notification = false
  1227. HWP activity window = false
  1228. HWP energy performance preference = false
  1229. HWP package level request = false
  1230. HDC base registers = false
  1231. digital thermometer thresholds = 0x2 (2)
  1232. ACNT/MCNT supported performance measure = true
  1233. ACNT2 available = false
  1234. performance-energy bias capability = true
  1235. extended feature flags (7):
  1236. FSGSBASE instructions = true
  1237. IA32_TSC_ADJUST MSR supported = true
  1238. SGX: Software Guard Extensions supported = false
  1239. BMI instruction = true
  1240. HLE hardware lock elision = false
  1241. AVX2: advanced vector extensions 2 = true
  1242. FDP_EXCPTN_ONLY = false
  1243. SMEP supervisor mode exec protection = true
  1244. BMI2 instructions = true
  1245. enhanced REP MOVSB/STOSB = true
  1246. INVPCID instruction = true
  1247. RTM: restricted transactional memory = false
  1248. QM: quality of service monitoring = false
  1249. deprecated FPU CS/DS = true
  1250. intel memory protection extensions = false
  1251. PQE: platform quality of service enforce = false
  1252. AVX512F: AVX-512 foundation instructions = false
  1253. AVX512DQ: double & quadword instructions = false
  1254. RDSEED instruction = false
  1255. ADX instructions = false
  1256. SMAP: supervisor mode access prevention = false
  1257. AVX512IFMA: fused multiply add = false
  1258. CLFLUSHOPT instruction = false
  1259. CLWB instruction = false
  1260. Intel processor trace = false
  1261. AVX512PF: prefetch instructions = false
  1262. AVX512ER: exponent & reciprocal instrs = false
  1263. AVX512CD: conflict detection instrs = false
  1264. SHA instructions = false
  1265. AVX512BW: byte & word instructions = false
  1266. AVX512VL: vector length = false
  1267. PREFETCHWT1 = false
  1268. AVX512VBMI: vector byte manipulation = false
  1269. UMIP: user-mode instruction prevention = false
  1270. PKU protection keys for user-mode = false
  1271. OSPKE CR4.PKE and RDPKRU/WRPKRU = false
  1272. BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
  1273. RDPID: read processor D supported = false
  1274. SGX_LC: SGX launch config supported = false
  1275. AVX512_4VNNIW: neural network instrs = false
  1276. AVX512_4FMAPS: multiply acc single prec = false
  1277. Direct Cache Access Parameters (9):
  1278. PLATFORM_DCA_CAP MSR bits = 0
  1279. Architecture Performance Monitoring Features (0xa/eax):
  1280. version ID = 0x3 (3)
  1281. number of counters per logical processor = 0x4 (4)
  1282. bit width of counter = 0x30 (48)
  1283. length of EBX bit vector = 0x7 (7)
  1284. Architecture Performance Monitoring Features (0xa/ebx):
  1285. core cycle event not available = false
  1286. instruction retired event not available = false
  1287. reference cycles event not available = false
  1288. last-level cache ref event not available = false
  1289. last-level cache miss event not avail = false
  1290. branch inst retired event not available = false
  1291. branch mispred retired event not avail = false
  1292. Architecture Performance Monitoring Features (0xa/edx):
  1293. number of fixed counters = 0x3 (3)
  1294. bit width of fixed counters = 0x30 (48)
  1295. x2APIC features / processor topology (0xb):
  1296. --- level 0 (thread) ---
  1297. bits to shift APIC ID to get next = 0x1 (1)
  1298. logical processors at this level = 0x2 (2)
  1299. level number = 0x0 (0)
  1300. level type = thread (1)
  1301. extended APIC ID = 3
  1302. --- level 1 (core) ---
  1303. bits to shift APIC ID to get next = 0x4 (4)
  1304. logical processors at this level = 0x4 (4)
  1305. level number = 0x1 (1)
  1306. level type = core (2)
  1307. extended APIC ID = 3
  1308. XSAVE features (0xd/0):
  1309. XCR0 lower 32 bits valid bit field mask = 0x00000007
  1310. XCR0 upper 32 bits valid bit field mask = 0x00000000
  1311. XCR0 supported: x87 state = true
  1312. XCR0 supported: SSE state = true
  1313. XCR0 supported: AVX state = true
  1314. XCR0 supported: MPX BNDREGS = false
  1315. XCR0 supported: MPX BNDCSR = false
  1316. XCR0 supported: AVX-512 opmask = false
  1317. XCR0 supported: AVX-512 ZMM_Hi256 = false
  1318. XCR0 supported: AVX-512 Hi16_ZMM = false
  1319. IA32_XSS supported: PT state = false
  1320. XCR0 supported: PKRU state = false
  1321. bytes required by fields in XCR0 = 0x00000340 (832)
  1322. bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
  1323. XSAVE features (0xd/1):
  1324. XSAVEOPT instruction = true
  1325. XSAVEC instruction = false
  1326. XGETBV instruction = false
  1327. XSAVES/XRSTORS instructions = false
  1328. SAVE area size in bytes = 0x00000000 (0)
  1329. IA32_XSS lower 32 bits valid bit field mask = 0x00000000
  1330. IA32_XSS upper 32 bits valid bit field mask = 0x00000000
  1331. AVX/YMM features (0xd/2):
  1332. AVX/YMM save state byte size = 0x00000100 (256)
  1333. AVX/YMM save state byte offset = 0x00000240 (576)
  1334. supported in IA32_XSS or XCR0 = XCR0 (user state)
  1335. 64-byte alignment in compacted XSAVE = false
  1336. extended feature flags (0x80000001/edx):
  1337. SYSCALL and SYSRET instructions = true
  1338. execution disable = true
  1339. 1-GB large page support = true
  1340. RDTSCP = true
  1341. 64-bit extensions technology available = true
  1342. Intel feature flags (0x80000001/ecx):
  1343. LAHF/SAHF supported in 64-bit mode = true
  1344. LZCNT advanced bit manipulation = true
  1345. 3DNow! PREFETCH/PREFETCHW instructions = false
  1346. brand = "Intel(R) Core(TM) i5-4250U CPU @ 1.30GHz"
  1347. L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
  1348. instruction # entries = 0x0 (0)
  1349. instruction associativity = 0x0 (0)
  1350. data # entries = 0x0 (0)
  1351. data associativity = 0x0 (0)
  1352. L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
  1353. instruction # entries = 0x0 (0)
  1354. instruction associativity = 0x0 (0)
  1355. data # entries = 0x0 (0)
  1356. data associativity = 0x0 (0)
  1357. L1 data cache information (0x80000005/ecx):
  1358. line size (bytes) = 0x0 (0)
  1359. lines per tag = 0x0 (0)
  1360. associativity = 0x0 (0)
  1361. size (KB) = 0x0 (0)
  1362. L1 instruction cache information (0x80000005/edx):
  1363. line size (bytes) = 0x0 (0)
  1364. lines per tag = 0x0 (0)
  1365. associativity = 0x0 (0)
  1366. size (KB) = 0x0 (0)
  1367. L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
  1368. instruction # entries = 0x0 (0)
  1369. instruction associativity = L2 off (0)
  1370. data # entries = 0x0 (0)
  1371. data associativity = L2 off (0)
  1372. L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
  1373. instruction # entries = 0x0 (0)
  1374. instruction associativity = L2 off (0)
  1375. data # entries = 0x0 (0)
  1376. data associativity = L2 off (0)
  1377. L2 unified cache information (0x80000006/ecx):
  1378. line size (bytes) = 0x40 (64)
  1379. lines per tag = 0x0 (0)
  1380. associativity = 8-way (6)
  1381. size (KB) = 0x100 (256)
  1382. L3 cache information (0x80000006/edx):
  1383. line size (bytes) = 0x0 (0)
  1384. lines per tag = 0x0 (0)
  1385. associativity = L2 off (0)
  1386. size (in 512KB units) = 0x0 (0)
  1387. Advanced Power Management Features (0x80000007/edx):
  1388. temperature sensing diode = false
  1389. frequency ID (FID) control = false
  1390. voltage ID (VID) control = false
  1391. thermal trip (TTP) = false
  1392. thermal monitor (TM) = false
  1393. software thermal control (STC) = false
  1394. 100 MHz multiplier control = false
  1395. hardware P-State control = false
  1396. TscInvariant = true
  1397. Physical Address and Linear Address Size (0x80000008/eax):
  1398. maximum physical address bits = 0x27 (39)
  1399. maximum linear (virtual) address bits = 0x30 (48)
  1400. maximum guest physical address bits = 0x0 (0)
  1401. Logical CPU cores (0x80000008/ecx):
  1402. number of CPU cores - 1 = 0x0 (0)
  1403. ApicIdCoreIdSize = 0x0 (0)
  1404. (multi-processing synth): multi-core (c=2), hyper-threaded (t=2)
  1405. (multi-processing method): Intel leaf 0xb
  1406. (APIC widths synth): CORE_width=4 SMT_width=1
  1407. (APIC synth): PKG_ID=0 CORE_ID=1 SMT_ID=1
  1408. (synth) = Intel Mobile Core i3-4000Y / Mobile Core i5-4000Y / Mobile Core i7-4000Y / Mobile Pentium 3500U/3600U/3500Y / Mobile Celeron 2900U (Mobile U/Y) (Haswell), 22nm
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