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- module triangle (clk, reset, nt, xi, yi, busy, po, xo, yo);
- input clk, reset, nt;
- input [2:0] xi, yi;
- output reg busy, po;
- output [2:0] xo, yo;
- reg [2:0] X[2:0];
- reg [2:0] Y[2:0];
- reg [2:0] X_ptr, Y_ptr;
- reg [3:0] state;
- wire [7:0] r1, r2;
- assign xo = X_ptr;
- assign yo = Y_ptr;
- assign r1=(X_ptr-X[0]+3'h1)*(Y[2]-Y[0]);
- // x1 - (x + 1)
- assign r2=(X[2]-X[0])*(Y_ptr - Y[0]);
- always@(posedge clk or posedge reset) begin
- if(reset) begin
- {X[2],X[1],X[0]} <= 9'h0;
- {Y[2],Y[1],Y[0]} <= 9'h0;
- busy <= 1'h0;
- po <= 1'h0;
- X_ptr <= 3'h0;
- Y_ptr <= 3'h0;
- state <= 4'h0;
- end
- else begin
- case(state)
- 4'h0:
- begin
- if(nt) begin
- X[0] <= xi;
- Y[0] <= yi;
- X_ptr <= xi[0];
- Y_ptr <= yi[0];
- busy <= 1'h1;
- state <= 4'h1;
- end
- end
- 4'h1:
- begin
- X[1] <= xi;
- Y[1] <= yi;
- state <= 4'h2;
- end
- 4'h2:
- begin
- X[2] <= xi;
- Y[2] <= yi;
- po <= 1'h1;
- state <= 4'h3;
- end
- 4'h3:
- begin
- if( (X_ptr==X[2]) & (Y_ptr==Y[2]))
- begin
- state <= 4'h4;
- po <= 1'h0;
- end
- else if (X_ptr == X[1])
- begin
- po <= 1'h0;
- X_ptr <= X[0];
- Y_ptr <= Y_ptr+3'h1;
- end
- else
- begin
- po <= (r1 >= r2)?1'h1:1'h0; // if the point is now locate at left of scale
- X_ptr <= X_ptr+3'h1;
- end
- end
- 4'h4:
- begin
- busy <= 1'h0;
- state <= 4'h0;
- end
- endcase
- end
- end
- endmodule
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