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ARM Design feedback response

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Mar 12th, 2013
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  1. 4. I'm using 0603s like the evaluation board I have from NXP (LPC4330-Xplorer from NGX Technologies)
  2. I can easily change over to 0805s without any problems.
  3.  
  4. 5. I'm using the SMSC LAN8720 Ethernet PHY IC. My Ethernet design is based on the reference design and documentation
  5. provided by SMSC for the LAN8720:
  6. http://www.smsc.com/Products/Ethernet_and_Embedded_Networking/Ethernet_Transceivers/LAN8710A_LAN8720A
  7. http://www.smsc.com/index.php?tid=149&pid=95
  8.  
  9. I did my best to clone the evaluation board while implementing equal length tracing and differential pairing
  10. where appropriate. When it came to connecting the PHY to the LPC4337 I used the schematic for the evaluation
  11. board I have : https://www.dropbox.com/s/t0vuxc7pruixdb7/LPC4330_Xplorer_schematic.pdf
  12. The schematic shows that the crystal's output connects to both the PHY and the LPC4337, I thought it was weird
  13. myself but this is the first Ethernet design I have ever done so I chose to stick with the reference design.
  14. I would appreciated your thoughts on it if you have wish to look at the links, I understand if you are busy.
  15.  
  16.  
  17. 7. The 12mm spacing between the PHY and the crystal was specified in the SMSC reference design specifications.
  18.  
  19. 9. this board is designed to mimic the functionality of an Arduino styled board, that being said do I need to put bypass
  20. capacitors on all the pins broken out to the pin header connectors?
  21.  
  22. 13. There are only a few places where vias are close together, mostly the places where large groups of signals
  23. are being broken out of the LPC4337 and traveling to the same place. Could this be seriously problematic? Is it
  24. bad to group vias this way when breaking out a lot of pins? I designed things this way by examining other PCB
  25. designs, mainly the Arduino DUE which uses a Cortex M3
  26.  
  27. 15. What constitutes proper signal termination on MII signals between the PHY and MAC? I apologize this is
  28. my first Ethernet design.
  29.  
  30. 16. The layers are stacked accordingly: Top Signals > Ground Plane > Power Plane > Bottom Layer signals.
  31. I tried my best to keep sensitive/high speed signals on the top layer such as Ethernet and USB. Most of
  32. the bottom layer signals are GPIO, I only ever ran sensitive signals on the bottom layer when I had
  33. no other choice to but to put them on the bottom.
  34.  
  35. 17. I'm looking into the traces running over gaps in the power planes, some of these signals would be
  36. very difficult to reroute. Is it ok to run say LED/GPIO control signals but bad to run say a USB 2.0 signal?
  37.  
  38.  
  39. 18. There is only a signal ground. None of the screw holes attach to any sort of ground they are mere just holes.
  40. Although I guess the metal housing on the USB and ethernet connectors could be considered chassis ground, making
  41. that consideration the USB housing is already connected through a ferrite bead but the ethernet is not. I can change
  42. this very easily.
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