// mac_test.v - demonstrate SB_MAC16 synth bug
// 03-21-21 E. Brombaugh

`default_nettype none

module mac_test(
    input clk,
    input signed [15:0] a0, b0, a1, b1,
    //output signed [31:0] m0,  // enabling this prevents removal of m0=a0*b0 cell
    output reg signed [31:0] sum
);
    // sum of products
    reg signed [31:0] m0, m1;
    always @(posedge clk)
    begin
        m0 <= a0 * b0;
        m1 <= a1 * b1;
        sum <= m0 + m1;
    end
endmodule