`timescale 1ns/1ps

module test();

parameter data_w=8,addr_w=5;

reg clock,reset,write_enable,read_enable;
reg [data_w-1:0] data_in;
wire empty,full;
wire [addr_w:0] fifo_counter;
wire [data_w-1:0] data_out;

initial begin
  clock=0;
  forever #1 clock=!clock;
end

integer idx;

initial begin
  reset=0;
  #2
  reset=1;
  write_enable=1;
  for(idx=0;idx<=2**addr_w;idx=idx+1) begin
  data_in=idx;
  #2;
  end
  write_enable=0;
  read_enable=1;
  for(idx=0;idx<=2**addr_w;idx=idx+1) begin
  #2;
  end
  read_enable=0;
  #10 $stop();
end

fifo #(.data_w(data_w),.addr_w(addr_w)) dut
(.clock(clock),
.reset(reset),
.write_enable(write_enable),
.read_enable(read_enable),
.data_in(data_in),
.empty(empty),
.full(full),
.fifo_counter(fifo_counter),
.data_out(data_out)
);

endmodule