hw3 dtb1

/dts-v1/;

/ {
	compatible = "turbo,trav-eval\0turbo,trav";
	interrupt-parent = < 0x01 >;
	#address-cells = < 0x02 >;
	#size-cells = < 0x02 >;
	model = "Trav Eval board based on TRAV SoC Rev A0";

	aliases {
		pinctrl0 = "/soc/pinctrl@15020000";
		pinctrl1 = "/soc/pinctrl@141F0000";
		pinctrl2 = "/soc/pinctrl@114F0000";
		spi0 = "/soc/spi@14140000";
		spi1 = "/soc/spi@14150000";
		spi2 = "/soc/spi@14160000";
		eth0 = "/soc/ethernet@15300000";
		eth1 = "/soc/ethernet@14300000";
		pcierc0 = "/soc/pcie0_rc@16A00000";
		pcieep0 = "/soc/pcie0_ep@16A00000";
		pcierc1 = "/soc/pcie1_rc@16B00000";
		pcieep1 = "/soc/pcie1_ep@16B00000";
		pcierc2 = "/soc/pcie4_rc@15400000";
		pcieep2 = "/soc/pcie4_ep@15400000";
		pciephy0 = "/soc/pcie-phy@15080000";
		pciephy1 = "/soc/pcie-phy@16880000";
		dprx0 = "/soc/dprx0@14ec0000";
		dprx1 = "/soc/dprx1@14e80000";
		dprx2 = "/soc/dprx2@14cc0000";
		dprx3 = "/soc/dprx3@14c80000";
		csis0 = "/soc/csis0@0x12640000";
		csis1 = "/soc/csis1@0x12650000";
		csis2 = "/soc/csis2@0x12660000";
		csis3 = "/soc/csis3@0x12670000";
		csis4 = "/soc/csis4@0x12680000";
		csis5 = "/soc/csis5@0x12690000";
		csis6 = "/soc/csis6@0x126A0000";
		csis7 = "/soc/csis7@0x126B0000";
		csis8 = "/soc/csis8@0x126C0000";
		csis9 = "/soc/csis9@0x126D0000";
		csis10 = "/soc/csis10@0x126E0000";
		csis11 = "/soc/csis11@0x126F0000";
		tmuctrl0 = "/soc/tmu@10180000";
		tmuctrl1 = "/soc/tmu@10184000";
		tmuctrl2 = "/soc/tmu@10188000";
		tmuctrl3 = "/soc/tmu@1018C000";
		tmuctrl4 = "/soc/tmu@10190000";
		tdm0 = "/soc/tdm@140E0000";
		watchdog0 = "/soc/watchdog@100A0000";
		watchdog1 = "/soc/watchdog@100B0000";
		watchdog2 = "/soc/watchdog@100C0000";
		serial0 = "/soc/serial@14180000";
		serial1 = "/soc/serial@14190000";
	};

	cpus {
		#address-cells = < 0x02 >;
		#size-cells = < 0x00 >;

		cpu-map {

			cluster0 {

				core0 {
					cpu = < 0x02 >;
				};

				core1 {
					cpu = < 0x03 >;
				};

				core2 {
					cpu = < 0x04 >;
				};

				core3 {
					cpu = < 0x05 >;
				};
			};

			cluster1 {

				core0 {
					cpu = < 0x06 >;
				};

				core1 {
					cpu = < 0x07 >;
				};

				core2 {
					cpu = < 0x08 >;
				};

				core3 {
					cpu = < 0x09 >;
				};
			};

			cluster2 {

				core0 {
					cpu = < 0x0a >;
				};

				core1 {
					cpu = < 0x0b >;
				};

				core2 {
					cpu = < 0x0c >;
				};

				core3 {
					cpu = < 0x0d >;
				};
			};
		};

		cpu@000 {
			device_type = "cpu";
			compatible = "arm,cortex-a72\0arm,armv8";
			reg = < 0x00 0x00 >;
			enable-method = "psci";
			clocks = < 0x0e 0x01 0x0e 0x02 0x0e 0x03 0x0e 0x04 >;
			clock-names = "fout_pll_cpucl\0mout_cpucl_pll\0mout_cpucl_clk_cluster_clk_mux\0mout_cpucl_switchclk_mux";
			clock-frequency = < 0x8f0d1800 >;
			cpu-supply = < 0x0f >;
			operating-points-v2 = < 0x10 >;
			#cooling-cells = < 0x02 >;
			cpu-idle-states = < 0x11 >;
			next-level-cache = < 0x12 >;
			linux,phandle = < 0x02 >;
			phandle = < 0x02 >;
		};

		cpu@001 {
			device_type = "cpu";
			compatible = "arm,cortex-a72\0arm,armv8";
			reg = < 0x00 0x01 >;
			enable-method = "psci";
			clocks = < 0x0e 0x01 0x0e 0x02 0x0e 0x03 0x0e 0x04 >;
			clock-names = "fout_pll_cpucl\0mout_cpucl_pll\0mout_cpucl_clk_cluster_clk_mux\0mout_cpucl_switchclk_mux";
			clock-frequency = < 0x8f0d1800 >;
			cpu-supply = < 0x0f >;
			operating-points-v2 = < 0x10 >;
			cpu-idle-states = < 0x11 >;
			next-level-cache = < 0x12 >;
			linux,phandle = < 0x03 >;
			phandle = < 0x03 >;
		};

		cpu@002 {
			device_type = "cpu";
			compatible = "arm,cortex-a72\0arm,armv8";
			reg = < 0x00 0x02 >;
			enable-method = "psci";
			clocks = < 0x0e 0x01 0x0e 0x02 0x0e 0x03 0x0e 0x04 >;
			clock-names = "fout_pll_cpucl\0mout_cpucl_pll\0mout_cpucl_clk_cluster_clk_mux\0mout_cpucl_switchclk_mux";
			clock-frequency = < 0x8f0d1800 >;
			cpu-supply = < 0x0f >;
			operating-points-v2 = < 0x10 >;
			cpu-idle-states = < 0x11 >;
			next-level-cache = < 0x12 >;
			linux,phandle = < 0x04 >;
			phandle = < 0x04 >;
		};

		cpu@003 {
			device_type = "cpu";
			compatible = "arm,cortex-a72\0arm,armv8";
			reg = < 0x00 0x03 >;
			enable-method = "psci";
			clocks = < 0x0e 0x01 0x0e 0x02 0x0e 0x03 0x0e 0x04 >;
			clock-names = "fout_pll_cpucl\0mout_cpucl_pll\0mout_cpucl_clk_cluster_clk_mux\0mout_cpucl_switchclk_mux";
			clock-frequency = < 0x8f0d1800 >;
			cpu-supply = < 0x0f >;
			operating-points-v2 = < 0x10 >;
			cpu-idle-states = < 0x11 >;
			next-level-cache = < 0x12 >;
			linux,phandle = < 0x05 >;
			phandle = < 0x05 >;
		};

		cpu@100 {
			device_type = "cpu";
			compatible = "arm,cortex-a72\0arm,armv8";
			reg = < 0x00 0x100 >;
			enable-method = "psci";
			clocks = < 0x0e 0x01 0x0e 0x02 0x0e 0x03 0x0e 0x04 >;
			clock-names = "fout_pll_cpucl\0mout_cpucl_pll\0mout_cpucl_clk_cluster_clk_mux\0mout_cpucl_switchclk_mux";
			clock-frequency = < 0x8f0d1800 >;
			cpu-supply = < 0x0f >;
			operating-points-v2 = < 0x10 >;
			#cooling-cells = < 0x02 >;
			cpu-idle-states = < 0x11 >;
			next-level-cache = < 0x12 >;
			linux,phandle = < 0x06 >;
			phandle = < 0x06 >;
		};

		cpu@101 {
			device_type = "cpu";
			compatible = "arm,cortex-a72\0arm,armv8";
			reg = < 0x00 0x101 >;
			enable-method = "psci";
			clocks = < 0x0e 0x01 0x0e 0x02 0x0e 0x03 0x0e 0x04 >;
			clock-names = "fout_pll_cpucl\0mout_cpucl_pll\0mout_cpucl_clk_cluster_clk_mux\0mout_cpucl_switchclk_mux";
			clock-frequency = < 0x8f0d1800 >;
			cpu-supply = < 0x0f >;
			operating-points-v2 = < 0x10 >;
			cpu-idle-states = < 0x11 >;
			next-level-cache = < 0x12 >;
			linux,phandle = < 0x07 >;
			phandle = < 0x07 >;
		};

		cpu@102 {
			device_type = "cpu";
			compatible = "arm,cortex-a72\0arm,armv8";
			reg = < 0x00 0x102 >;
			enable-method = "psci";
			clocks = < 0x0e 0x01 0x0e 0x02 0x0e 0x03 0x0e 0x04 >;
			clock-names = "fout_pll_cpucl\0mout_cpucl_pll\0mout_cpucl_clk_cluster_clk_mux\0mout_cpucl_switchclk_mux";
			clock-frequency = < 0x8f0d1800 >;
			cpu-supply = < 0x0f >;
			operating-points-v2 = < 0x10 >;
			cpu-idle-states = < 0x11 >;
			next-level-cache = < 0x12 >;
			linux,phandle = < 0x08 >;
			phandle = < 0x08 >;
		};

		cpu@103 {
			device_type = "cpu";
			compatible = "arm,cortex-a72\0arm,armv8";
			reg = < 0x00 0x103 >;
			enable-method = "psci";
			clocks = < 0x0e 0x01 0x0e 0x02 0x0e 0x03 0x0e 0x04 >;
			clock-names = "fout_pll_cpucl\0mout_cpucl_pll\0mout_cpucl_clk_cluster_clk_mux\0mout_cpucl_switchclk_mux";
			clock-frequency = < 0x8f0d1800 >;
			cpu-supply = < 0x0f >;
			operating-points-v2 = < 0x10 >;
			cpu-idle-states = < 0x11 >;
			next-level-cache = < 0x12 >;
			linux,phandle = < 0x09 >;
			phandle = < 0x09 >;
		};

		cpu@200 {
			device_type = "cpu";
			compatible = "arm,cortex-a72\0arm,armv8";
			reg = < 0x00 0x200 >;
			enable-method = "psci";
			clocks = < 0x0e 0x01 0x0e 0x02 0x0e 0x03 0x0e 0x04 >;
			clock-names = "fout_pll_cpucl\0mout_cpucl_pll\0mout_cpucl_clk_cluster_clk_mux\0mout_cpucl_switchclk_mux";
			clock-frequency = < 0x8f0d1800 >;
			cpu-supply = < 0x0f >;
			operating-points-v2 = < 0x10 >;
			#cooling-cells = < 0x02 >;
			cpu-idle-states = < 0x11 >;
			next-level-cache = < 0x12 >;
			linux,phandle = < 0x0a >;
			phandle = < 0x0a >;
		};

		cpu@201 {
			device_type = "cpu";
			compatible = "arm,cortex-a72\0arm,armv8";
			reg = < 0x00 0x201 >;
			enable-method = "psci";
			clocks = < 0x0e 0x01 0x0e 0x02 0x0e 0x03 0x0e 0x04 >;
			clock-names = "fout_pll_cpucl\0mout_cpucl_pll\0mout_cpucl_clk_cluster_clk_mux\0mout_cpucl_switchclk_mux";
			clock-frequency = < 0x8f0d1800 >;
			cpu-supply = < 0x0f >;
			operating-points-v2 = < 0x10 >;
			cpu-idle-states = < 0x11 >;
			next-level-cache = < 0x12 >;
			linux,phandle = < 0x0b >;
			phandle = < 0x0b >;
		};

		cpu@202 {
			device_type = "cpu";
			compatible = "arm,cortex-a72\0arm,armv8";
			reg = < 0x00 0x202 >;
			enable-method = "psci";
			clocks = < 0x0e 0x01 0x0e 0x02 0x0e 0x03 0x0e 0x04 >;
			clock-names = "fout_pll_cpucl\0mout_cpucl_pll\0mout_cpucl_clk_cluster_clk_mux\0mout_cpucl_switchclk_mux";
			clock-frequency = < 0x8f0d1800 >;
			cpu-supply = < 0x0f >;
			operating-points-v2 = < 0x10 >;
			cpu-idle-states = < 0x11 >;
			next-level-cache = < 0x12 >;
			linux,phandle = < 0x0c >;
			phandle = < 0x0c >;
		};

		cpu@203 {
			device_type = "cpu";
			compatible = "arm,cortex-a72\0arm,armv8";
			reg = < 0x00 0x203 >;
			enable-method = "psci";
			clocks = < 0x0e 0x01 0x0e 0x02 0x0e 0x03 0x0e 0x04 >;
			clock-names = "fout_pll_cpucl\0mout_cpucl_pll\0mout_cpucl_clk_cluster_clk_mux\0mout_cpucl_switchclk_mux";
			clock-frequency = < 0x8f0d1800 >;
			cpu-supply = < 0x0f >;
			operating-points-v2 = < 0x10 >;
			cpu-idle-states = < 0x11 >;
			next-level-cache = < 0x12 >;
			linux,phandle = < 0x0d >;
			phandle = < 0x0d >;
		};

		idle-states {
			entry-method = "arm,psci";

			cpu-sleep {
				idle-state-name = "c2";
				compatible = "arm,idle-state";
				local-timer-stop;
				arm,psci-suspend-param = < 0x10000 >;
				entry-latency-us = < 0x1e >;
				exit-latency-us = < 0x4b >;
				min-residency-us = < 0x12c >;
				status = "okay";
				linux,phandle = < 0x11 >;
				phandle = < 0x11 >;
			};
		};

		l2-cache0 {
			compatible = "cache";
			linux,phandle = < 0x12 >;
			phandle = < 0x12 >;
		};
	};

	arm-pmu {
		compatible = "arm,armv8-pmuv3";
		interrupts = < 0x00 0x164 0x04 0x00 0x165 0x04 0x00 0x166 0x04 0x00 0x167 0x04 0x00 0x172 0x04 0x00 0x173 0x04 0x00 0x174 0x04 0x00 0x175 0x04 0x00 0x180 0x04 0x00 0x181 0x04 0x00 0x182 0x04 0x00 0x183 0x04 >;
		interrupt-affinity = < 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b 0x0c 0x0d >;
	};

	cpu_opp_table {
		compatible = "operating-points-v2";
		opp-shared;
		linux,phandle = < 0x10 >;
		phandle = < 0x10 >;

		opp00 {
			opp-hz = < 0x00 0x83215600 >;
			opp-microvolt = < 0x10c8e0 >;
			opp-microvolt-asv1 = < 0x10bd28 >;
			opp-microvolt-asv2 = < 0xff9d8 >;
			opp-microvolt-asv3 = < 0xf3688 >;
			opp-microvolt-asv4 = < 0xe86c0 >;
			clock-latency-ns = < 0x30d40 >;
		};

		opp01 {
			opp-hz = < 0x00 0x77359400 >;
			opp-microvolt = < 0x100590 >;
			opp-microvolt-asv1 = < 0xfb770 >;
			opp-microvolt-asv2 = < 0xf2ad0 >;
			opp-microvolt-asv3 = < 0xe9e30 >;
			opp-microvolt-asv4 = < 0xe2518 >;
			clock-latency-ns = < 0x30d40 >;
		};

		opp02 {
			opp-hz = < 0x00 0x5f5e1000 >;
			opp-microvolt = < 0xe7ef0 >;
			opp-microvolt-asv1 = < 0xe2900 >;
			opp-microvolt-asv2 = < 0xd90a8 >;
			opp-microvolt-asv3 = < 0xcf850 >;
			opp-microvolt-asv4 = < 0xc6f98 >;
			clock-latency-ns = < 0x30d40 >;
		};
	};

	trip0_opp_table {
		compatible = "operating-points-v2";
		linux,phandle = < 0xee >;
		phandle = < 0xee >;

		opp-2000000000 {
			opp-hz = < 0x00 0x77359400 >;
			opp-microvolt = < 0x106738 0x106738 0x106738 >;
			opp-microvolt-asv1 = < 0x102ca0 0x102ca0 0x102ca0 >;
			opp-microvolt-asv2 = < 0xf84a8 0xf84a8 0xf84a8 >;
			opp-microvolt-asv3 = < 0xea600 0xea600 0xea600 >;
			opp-microvolt-asv4 = < 0xde698 0xde698 0xde698 >;
			clock-latency-ns = < 0x30d40 >;
		};

		opp-1800000000 {
			opp-hz = < 0x00 0x6b49d200 >;
			opp-microvolt = < 0xeffd8 0xeffd8 0x106738 >;
			opp-microvolt-asv1 = < 0xebd70 0xebd70 0x102ca0 >;
			opp-microvolt-asv2 = < 0xe4458 0xe4458 0xf84a8 >;
			opp-microvolt-asv3 = < 0xd90a8 0xd90a8 0xea600 >;
			opp-microvolt-asv4 = < 0xcec98 0xcec98 0xde698 >;
			clock-latency-ns = < 0x30d40 >;
		};

		opp-1700000000 {
			opp-hz = < 0x00 0x6553f100 >;
			opp-microvolt = < 0xe7338 0xe7338 0x106738 >;
			opp-microvolt-asv1 = < 0xe30d0 0xe30d0 0x102ca0 >;
			opp-microvolt-asv2 = < 0xde2b0 0xde2b0 0xf84a8 >;
			opp-microvolt-asv3 = < 0xd36d0 0xd36d0 0xea600 >;
			opp-microvolt-asv4 = < 0xc96a8 0xc96a8 0xde698 >;
			clock-latency-ns = < 0x30d40 >;
		};

		opp-1350000000 {
			opp-hz = < 0x00 0x50775d80 >;
			opp-microvolt = < 0xc8708 0xc8708 0x106738 >;
			opp-microvolt-asv1 = < 0xc5058 0xc5058 0x102ca0 >;
			opp-microvolt-asv2 = < 0xc3500 0xc3500 0xf84a8 >;
			opp-microvolt-asv3 = < 0xbbfd0 0xbbfd0 0xea600 >;
			opp-microvolt-asv4 = < 0xb4aa0 0xb4aa0 0xde698 >;
			clock-latency-ns = < 0x30d40 >;
		};

		opp-106250000, {
			opp-hz = < 0x00 0x6553f10 >;
			opp-microvolt = < 0xe7338 0xe7338 0x106738 >;
			opp-microvolt-asv1 = < 0xe30d0 0xe30d0 0x102ca0 >;
			opp-microvolt-asv2 = < 0xde2b0 0xde2b0 0xf84a8 >;
			opp-microvolt-asv3 = < 0xd36d0 0xd36d0 0xea600 >;
			opp-microvolt-asv4 = < 0xc96a8 0xc96a8 0xde698 >;
			clock-latency-ns = < 0x30d40 >;
		};

		opp-84375000 {
			opp-hz = < 0x00 0x50775d8 >;
			opp-microvolt = < 0xc8708 0xc8708 0x106738 >;
			opp-microvolt-asv1 = < 0xc5058 0xc5058 0x102ca0 >;
			opp-microvolt-asv2 = < 0xc3500 0xc3500 0xf84a8 >;
			opp-microvolt-asv3 = < 0xbbfd0 0xbbfd0 0xea600 >;
			opp-microvolt-asv4 = < 0xb4aa0 0xb4aa0 0xde698 >;
			clock-latency-ns = < 0x30d40 >;
		};

		opp-62500000 {
			opp-hz = < 0x00 0x3b9aca0 >;
			opp-microvolt = < 0x106738 0x106738 0x106738 >;
			opp-microvolt-asv1 = < 0x102ca0 0x102ca0 0x102ca0 >;
			opp-microvolt-asv2 = < 0xf84a8 0xf84a8 0xf84a8 >;
			opp-microvolt-asv3 = < 0xea600 0xea600 0xea600 >;
			opp-microvolt-asv4 = < 0xde698 0xde698 0xde698 >;
			clock-latency-ns = < 0x30d40 >;
		};

		opp-56250000 {
			opp-hz = < 0x00 0x35a4e90 >;
			opp-microvolt = < 0xeffd8 0xeffd8 0x106738 >;
			opp-microvolt-asv1 = < 0xebd70 0xebd70 0x102ca0 >;
			opp-microvolt-asv2 = < 0xe4458 0xe4458 0xf84a8 >;
			opp-microvolt-asv3 = < 0xd90a8 0xd90a8 0xea600 >;
			opp-microvolt-asv4 = < 0xcec98 0xcec98 0xde698 >;
			clock-latency-ns = < 0x30d40 >;
		};
	};

	trip1_opp_table {
		compatible = "operating-points-v2";
		linux,phandle = < 0xf2 >;
		phandle = < 0xf2 >;

		opp-2000000000 {
			opp-hz = < 0x00 0x77359400 >;
			opp-microvolt = < 0x106738 0x106738 0x106738 >;
			opp-microvolt-asv1 = < 0x102ca0 0x102ca0 0x102ca0 >;
			opp-microvolt-asv2 = < 0xf84a8 0xf84a8 0xf84a8 >;
			opp-microvolt-asv3 = < 0xea600 0xea600 0xea600 >;
			opp-microvolt-asv4 = < 0xde698 0xde698 0xde698 >;
			clock-latency-ns = < 0x30d40 >;
		};

		opp-1800000000 {
			opp-hz = < 0x00 0x6b49d200 >;
			opp-microvolt = < 0xeffd8 0xeffd8 0x106738 >;
			opp-microvolt-asv1 = < 0xebd70 0xebd70 0x102ca0 >;
			opp-microvolt-asv2 = < 0xe4458 0xe4458 0xf84a8 >;
			opp-microvolt-asv3 = < 0xd90a8 0xd90a8 0xea600 >;
			opp-microvolt-asv4 = < 0xcec98 0xcec98 0xde698 >;
			clock-latency-ns = < 0x30d40 >;
		};

		opp-1700000000 {
			opp-hz = < 0x00 0x6553f100 >;
			opp-microvolt = < 0xe7338 0xe7338 0x106738 >;
			opp-microvolt-asv1 = < 0xe30d0 0xe30d0 0x102ca0 >;
			opp-microvolt-asv2 = < 0xde2b0 0xde2b0 0xf84a8 >;
			opp-microvolt-asv3 = < 0xd36d0 0xd36d0 0xea600 >;
			opp-microvolt-asv4 = < 0xc96a8 0xc96a8 0xde698 >;
			clock-latency-ns = < 0x30d40 >;
		};

		opp-1350000000 {
			opp-hz = < 0x00 0x50775d80 >;
			opp-microvolt = < 0xc8708 0xc8708 0x106738 >;
			opp-microvolt-asv1 = < 0xc5058 0xc5058 0x102ca0 >;
			opp-microvolt-asv2 = < 0xc3500 0xc3500 0xf84a8 >;
			opp-microvolt-asv3 = < 0xbbfd0 0xbbfd0 0xea600 >;
			opp-microvolt-asv4 = < 0xb4aa0 0xb4aa0 0xde698 >;
			clock-latency-ns = < 0x30d40 >;
		};

		opp-106250000, {
			opp-hz = < 0x00 0x6553f10 >;
			opp-microvolt = < 0xe7338 0xe7338 0x106738 >;
			opp-microvolt-asv1 = < 0xe30d0 0xe30d0 0x102ca0 >;
			opp-microvolt-asv2 = < 0xde2b0 0xde2b0 0xf84a8 >;
			opp-microvolt-asv3 = < 0xd36d0 0xd36d0 0xea600 >;
			opp-microvolt-asv4 = < 0xc96a8 0xc96a8 0xde698 >;
			clock-latency-ns = < 0x30d40 >;
		};

		opp-84375000 {
			opp-hz = < 0x00 0x50775d8 >;
			opp-microvolt = < 0xc8708 0xc8708 0x106738 >;
			opp-microvolt-asv1 = < 0xc5058 0xc5058 0x102ca0 >;
			opp-microvolt-asv2 = < 0xc3500 0xc3500 0xf84a8 >;
			opp-microvolt-asv3 = < 0xbbfd0 0xbbfd0 0xea600 >;
			opp-microvolt-asv4 = < 0xb4aa0 0xb4aa0 0xde698 >;
			clock-latency-ns = < 0x30d40 >;
		};

		opp-62500000 {
			opp-hz = < 0x00 0x3b9aca0 >;
			opp-microvolt = < 0x106738 0x106738 0x106738 >;
			opp-microvolt-asv1 = < 0x102ca0 0x102ca0 0x102ca0 >;
			opp-microvolt-asv2 = < 0xf84a8 0xf84a8 0xf84a8 >;
			opp-microvolt-asv3 = < 0xea600 0xea600 0xea600 >;
			opp-microvolt-asv4 = < 0xde698 0xde698 0xde698 >;
			clock-latency-ns = < 0x30d40 >;
		};

		opp-56250000 {
			opp-hz = < 0x00 0x35a4e90 >;
			opp-microvolt = < 0xeffd8 0xeffd8 0x106738 >;
			opp-microvolt-asv1 = < 0xebd70 0xebd70 0x102ca0 >;
			opp-microvolt-asv2 = < 0xe4458 0xe4458 0xf84a8 >;
			opp-microvolt-asv3 = < 0xd90a8 0xd90a8 0xea600 >;
			opp-microvolt-asv4 = < 0xcec98 0xcec98 0xde698 >;
			clock-latency-ns = < 0x30d40 >;
		};
	};

	psci {
		compatible = "arm,psci-1.0";
		method = "smc";
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = < 0x01 0x0d 0x08 0x01 0x0e 0x08 0x01 0x0b 0x08 0x01 0x0a 0x08 >;
	};

	reserved-memory {
		#address-cells = < 0x02 >;
		#size-cells = < 0x02 >;
		ranges;

		region@F0000000 {
			compatible = "shared-dma-pool";
			no-map;
			reg = < 0x00 0xf0000000 0x00 0x4000000 >;
			linux,phandle = < 0x68 >;
			phandle = < 0x68 >;
		};

		region@1a0000000 {
			compatible = "shared-dma-pool";
			reusable;
			reg = < 0x01 0xa0000000 0x00 0x20000000 >;
			alignment = < 0x200000 >;
			linux,phandle = < 0xea >;
			phandle = < 0xea >;
		};

		region@1c0000000 {
			compatible = "shared-dma-pool";
			reusable;
			reg = < 0x01 0xc0000000 0x00 0x80000000 >;
			alignment = < 0x200000 >;
			linux,phandle = < 0xe9 >;
			phandle = < 0xe9 >;
		};

		region@F4000000 {
			compatible = "shared-dma-pool";
			no-map;
			reg = < 0x00 0xf4000000 0x00 0x40000 >;
			linux,phandle = < 0x69 >;
			phandle = < 0x69 >;
		};

		ramoops@fffe0000 {
			compatible = "ramoops";
			reg = < 0x00 0xfffe0000 0x00 0x20000 >;
			record-size = < 0x10000 >;
			console-size = < 0x10000 >;
			no-dump-oops;
			no-map;
		};
	};

	soc {
		compatible = "simple-bus";
		#address-cells = < 0x01 >;
		#size-cells = < 0x01 >;
		ranges = < 0x00 0x00 0x00 0x18000000 >;

		iommu@12100000 {
			compatible = "arm,mmu-500";
			reg = < 0x12100000 0x10000 >;
			#iommu-cells = < 0x02 >;
			#global-interrupts = < 0x0b >;
			interrupts = < 0x00 0x141 0x04 0x00 0x142 0x04 0x00 0x15a 0x04 0x00 0x159 0x04 0x00 0x143 0x04 0x00 0x144 0x04 0x00 0x145 0x04 0x00 0x146 0x04 0x00 0x147 0x04 0x00 0x148 0x04 0x00 0x149 0x04 0x00 0x14a 0x04 0x00 0x14b 0x04 0x00 0x14c 0x04 0x00 0x14d 0x04 0x00 0x14e 0x04 0x00 0x14f 0x04 0x00 0x150 0x04 0x00 0x151 0x04 >;
			status = "okay";
			linux,phandle = < 0x67 >;
			phandle = < 0x67 >;
		};

		iommu@10200000 {
			compatible = "arm,mmu-500";
			reg = < 0x10200000 0x10000 >;
			#iommu-cells = < 0x02 >;
			#global-interrupts = < 0x07 >;
			interrupts = < 0x00 0x1b6 0x04 0x00 0x1b7 0x04 0x00 0x1c3 0x04 0x00 0x1c2 0x04 0x00 0x1b9 0x04 0x00 0x1ba 0x04 0x00 0x1bb 0x04 0x00 0x1be 0x04 0x00 0x1bf 0x04 0x00 0x1c0 0x04 0x00 0x1c1 0x04 >;
			status = "okay";
			linux,phandle = < 0x15 >;
			phandle = < 0x15 >;
		};

		iommu@11380000 {
			compatible = "arm,mmu-500";
			reg = < 0x11380000 0x10000 >;
			#iommu-cells = < 0x02 >;
			#global-interrupts = < 0x05 >;
			interrupts = < 0x00 0x46 0x04 0x00 0x45 0x04 0x00 0x42 0x04 0x00 0x41 0x04 0x00 0x47 0x04 0x00 0x43 0x04 0x00 0x44 0x04 >;
			status = "okay";
			linux,phandle = < 0xec >;
			phandle = < 0xec >;
		};

		iommu@11390000 {
			compatible = "arm,mmu-500";
			reg = < 0x11390000 0x10000 >;
			#iommu-cells = < 0x02 >;
			#global-interrupts = < 0x05 >;
			interrupts = < 0x00 0x4d 0x04 0x00 0x4c 0x04 0x00 0x49 0x04 0x00 0x48 0x04 0x00 0x4e 0x04 0x00 0x4a 0x04 0x00 0x4b 0x04 >;
			status = "okay";
			linux,phandle = < 0xf0 >;
			phandle = < 0xf0 >;
		};

		iommu@14900000 {
			compatible = "arm,mmu-500";
			reg = < 0x14900000 0x10000 >;
			#iommu-cells = < 0x02 >;
			#global-interrupts = < 0x05 >;
			interrupts = < 0x00 0xc5 0x04 0x00 0xc4 0x04 0x00 0xc1 0x04 0x00 0xc0 0x04 0x00 0xc6 0x04 0x00 0xc2 0x04 0x00 0xc3 0x04 >;
			status = "okay";
			linux,phandle = < 0x17 >;
			phandle = < 0x17 >;
		};

		iommu@15450000 {
			compatible = "arm,mmu-500";
			reg = < 0x15450000 0x10000 >;
			#iommu-cells = < 0x02 >;
			#global-interrupts = < 0x05 >;
			interrupts = < 0x00 0x64 0x04 0x00 0x63 0x04 0x00 0x60 0x04 0x00 0x5f 0x04 0x00 0x65 0x04 0x00 0x61 0x04 0x00 0x62 0x04 >;
			status = "okay";
			linux,phandle = < 0x5f >;
			phandle = < 0x5f >;
		};

		xxti {
			compatible = "fixed-clock";
			clock-output-names = "fin_pll";
			#clock-cells = < 0x00 >;
			clock-frequency = < 0x16e3600 >;
			linux,phandle = < 0x18 >;
			phandle = < 0x18 >;
		};

		interrupt-controller@10400000 {
			compatible = "arm,gic-v3";
			#interrupt-cells = < 0x03 >;
			interrupt-controller;
			reg = < 0x10400000 0x10000 0x10600000 0x200000 >;
			linux,phandle = < 0x01 >;
			phandle = < 0x01 >;
		};

		mali@14500000 {
			compatible = "arm,mali-midgard";
			reg = < 0x14500000 0x5000 >;
			interrupts = < 0x00 0x7a 0x04 0x00 0x7b 0x04 0x00 0x79 0x04 >;
			interrupt-names = "JOB\0MMU\0GPU";
			clocks = < 0x13 0x01 0x13 0x02 0x13 0x03 0x13 0x04 >;
			clock-names = "mout_clk_gpu_pll\0mout_clk_gpu_busd\0mout_clk_gpu_switch_user\0clk_gpu";
			system-coherency = < 0x01 >;
			status = "okay";
			broken-pwr-mode;
		};

		amba {
			compatible = "simple-bus";
			#address-cells = < 0x01 >;
			#size-cells = < 0x01 >;
			ranges;

			mdma@10100000 {
				compatible = "arm,pl330\0arm,primecell";
				reg = < 0x10100000 0x1000 >;
				interrupts = < 0x00 0x1a8 0x04 >;
				#dma-cells = < 0x01 >;
				#dma-channels = < 0x08 >;
				#dma-requests = < 0x20 >;
				clocks = < 0x14 0x01 >;
				clock-names = "apb_pclk";
				iommus = < 0x15 0x800 0x00 >;
				status = "okay";
			};

			mdma@10110000 {
				compatible = "arm,pl330\0arm,primecell";
				reg = < 0x10110000 0x1000 >;
				interrupts = < 0x00 0x1a9 0x04 >;
				#dma-cells = < 0x01 >;
				#dma-channels = < 0x08 >;
				#dma-requests = < 0x20 >;
				clocks = < 0x14 0x02 >;
				clock-names = "apb_pclk";
				iommus = < 0x15 0x801 0x00 >;
				status = "okay";
			};

			pdma@14280000 {
				compatible = "arm,pl330\0arm,primecell";
				reg = < 0x14280000 0x1000 >;
				interrupts = < 0x00 0xbe 0x04 >;
				#dma-cells = < 0x01 >;
				#dma-channels = < 0x08 >;
				#dma-requests = < 0x20 >;
				clocks = < 0x16 0x05 >;
				clock-names = "apb_pclk";
				iommus = < 0x17 0x02 0x00 >;
				status = "okay";
			};

			pdma@14290000 {
				compatible = "arm,pl330\0arm,primecell";
				reg = < 0x14290000 0x1000 >;
				interrupts = < 0x00 0xbf 0x04 >;
				#dma-cells = < 0x01 >;
				#dma-channels = < 0x08 >;
				#dma-requests = < 0x20 >;
				clocks = < 0x16 0x06 >;
				clock-names = "apb_pclk";
				iommus = < 0x17 0x01 0x00 >;
				status = "okay";
				linux,phandle = < 0x29 >;
				phandle = < 0x29 >;
			};
		};

		clock-controller@11C10000 {
			compatible = "turbo,trav-clock-cmu";
			reg = < 0x11c10000 0x3000 >;
			#clock-cells = < 0x01 >;
			clocks = < 0x18 >;
			clock-names = "fin_pll";
			status = "okay";
			linux,phandle = < 0x19 >;
			phandle = < 0x19 >;
		};

		clock-controller@14010000 {
			compatible = "turbo,trav-clock-peric\0syscon";
			reg = < 0x14010000 0x3000 >;
			#clock-cells = < 0x01 >;
			clocks = < 0x18 0x19 0x01 0x19 0x02 0x19 0x03 0x19 0x04 0x19 0x05 >;
			clock-names = "fin_pll\0dout_cmu_pll_shared0_div4\0dout_cmu_peric_shared1div36\0dout_cmu_peric_shared0div3_tbuclk\0dout_cmu_peric_shared0div20\0dout_cmu_peric_shared1div4_dmaclk";
			status = "okay";
			linux,phandle = < 0x16 >;
			phandle = < 0x16 >;
		};

		clock-controller@15010000 {
			compatible = "turbo,trav-clock-fsys0";
			reg = < 0x15010000 0x3000 >;
			#clock-cells = < 0x01 >;
			clocks = < 0x18 0x19 0x06 0x19 0x07 0x19 0x08 >;
			clock-names = "fin_pll\0dout_cmu_pll_shared0_div6\0dout_cmu_fsys0_shared1div4\0dout_cmu_fsys0_shared0div4";
			status = "okay";
			linux,phandle = < 0x5c >;
			phandle = < 0x5c >;
		};

		clock-controller@16810000 {
			compatible = "turbo,trav-clock-fsys1";
			reg = < 0x16810000 0x3000 >;
			#clock-cells = < 0x01 >;
			clocks = < 0x18 0x19 0x09 0x19 0x0a >;
			clock-names = "fin_pll\0dout_cmu_fsys1_shared0div8\0dout_cmu_fsys1_shared0div4";
			status = "okay";
			linux,phandle = < 0xae >;
			phandle = < 0xae >;
		};

		clock-controller@11310000 {
			compatible = "turbo,trav-clock-core_gt";
			reg = < 0x11310000 0x3000 >;
			#clock-cells = < 0x01 >;
			clocks = < 0x18 >;
			clock-names = "fin_pll";
			status = "disabled";
			linux,phandle = < 0x1a >;
			phandle = < 0x1a >;
		};

		clock-controller@11A10000 {
			compatible = "turbo,trav-clock-core_mifl";
			reg = < 0x11a10000 0x3000 >;
			#clock-cells = < 0x01 >;
			clocks = < 0x18 0x1a 0x01 >;
			clock-names = "fin_pll\0dout_core_gt_div_mif_switchclk";
			status = "disabled";
			linux,phandle = < 0x1b >;
			phandle = < 0x1b >;
		};

		clock-controller@11B10000 {
			compatible = "turbo,trav-clock-core_mifr";
			reg = < 0x11b10000 0x3000 >;
			#clock-cells = < 0x01 >;
			clocks = < 0x18 0x1a 0x01 >;
			clock-names = "fin_pll\0dout_core_gt_div_mif_switchclk";
			status = "disabled";
			linux,phandle = < 0x1c >;
			phandle = < 0x1c >;
		};

		clock-controller@11010000 {
			compatible = "turbo,trav-clock-cpucl";
			reg = < 0x11010000 0x3000 >;
			#clock-cells = < 0x01 >;
			clocks = < 0x18 0x0e 0x01 0x0e 0x02 0x0e 0x03 0x0e 0x04 0x19 0x0b >;
			clock-names = "fin_pll\0fout_pll_cpucl\0mout_cpucl_pll\0mout_cpucl_clk_cluster_clk_mux\0mout_cpucl_switchclk_mux\0cmu_cpucl_switch_gate";
			status = "okay";
			linux,phandle = < 0x0e >;
			phandle = < 0x0e >;
		};

		clock-controller@10010000 {
			compatible = "turbo,trav-clock-imem";
			reg = < 0x10010000 0x3000 >;
			#clock-cells = < 0x01 >;
			clocks = < 0x18 0x19 0x0c 0x19 0x0d 0x19 0x0e >;
			clock-names = "fin_pll\0dout_cmu_imem_tcuclk\0dout_cmu_imem_aclk\0dout_cmu_imem_dmaclk";
			status = "okay";
			linux,phandle = < 0x14 >;
			phandle = < 0x14 >;
		};

		clock-controller@11410000 {
			compatible = "turbo,trav-clock-pmu";
			reg = < 0x11410000 0x3000 >;
			#clock-cells = < 0x01 >;
			clocks = < 0x18 >;
			clock-names = "fin_pll";
			status = "disabled";
		};

		clock-controller@10810000 {
			compatible = "turbo,trav-clock-mif0";
			reg = < 0x10810000 0x3000 >;
			#clock-cells = < 0x01 >;
			clocks = < 0x18 0x1b 0x01 >;
			clock-names = "fin_pll\0mout_core_mifl_pll_mifl_clk";
			status = "disabled";
		};

		clock-controller@10910000 {
			compatible = "turbo,trav-clock-mif1";
			reg = < 0x10910000 0x3000 >;
			#clock-cells = < 0x01 >;
			clocks = < 0x18 0x1b 0x01 >;
			clock-names = "fin_pll\0mout_core_mifl_pll_mifl_clk";
			status = "disabled";
		};

		clock-controller@10A10000 {
			compatible = "turbo,trav-clock-mif2";
			reg = < 0x10a10000 0x3000 >;
			#clock-cells = < 0x01 >;
			clocks = < 0x18 0x1b 0x01 >;
			clock-names = "fin_pll\0mout_core_mifl_pll_mifl_clk";
			status = "disabled";
		};

		clock-controller@10B10000 {
			compatible = "turbo,trav-clock-mif3";
			reg = < 0x10b10000 0x3000 >;
			#clock-cells = < 0x01 >;
			clocks = < 0x18 0x1b 0x01 >;
			clock-names = "fin_pll\0mout_core_mifl_pll_mifl_clk";
			status = "disabled";
		};

		clock-controller@10C10000 {
			compatible = "turbo,trav-clock-mif4";
			reg = < 0x10c10000 0x3000 >;
			#clock-cells = < 0x01 >;
			clocks = < 0x18 0x1c 0x01 >;
			clock-names = "fin_pll\0mout_core_mifr_pll_mifr_clk";
			status = "disabled";
		};

		clock-controller@10D10000 {
			compatible = "turbo,trav-clock-mif5";
			reg = < 0x10d10000 0x3000 >;
			#clock-cells = < 0x01 >;
			clocks = < 0x18 0x1c 0x01 >;
			clock-names = "fin_pll\0mout_core_mifr_pll_mifr_clk";
			status = "disabled";
		};

		clock-controller@10E10000 {
			compatible = "turbo,trav-clock-mif6";
			reg = < 0x10e10000 0x3000 >;
			#clock-cells = < 0x01 >;
			clocks = < 0x18 0x1c 0x01 >;
			clock-names = "fin_pll\0mout_core_mifr_pll_mifr_clk";
			status = "disabled";
		};

		clock-controller@10F10000 {
			compatible = "turbo,trav-clock-mif7";
			reg = < 0x10f10000 0x3000 >;
			#clock-cells = < 0x01 >;
			clocks = < 0x18 0x1c 0x01 >;
			clock-names = "fin_pll\0mout_core_mifr_pll_mifr_clk";
			status = "disabled";
		};

		clock-controller@12810000 {
			compatible = "turbo,trav-clock-mfc";
			reg = < 0x12810000 0x3000 >;
			#clock-cells = < 0x01 >;
			clocks = < 0x18 >;
			clock-names = "fin_pll";
			status = "okay";
			linux,phandle = < 0x66 >;
			phandle = < 0x66 >;
		};

		clock-controller@12010000 {
			compatible = "turbo,trav-clock-isp";
			reg = < 0x12010000 0x3000 >;
			#clock-cells = < 0x01 >;
			clocks = < 0x18 0x19 0x0f >;
			clock-names = "fin_pll\0dout_cmu_isp_tcuclk";
			status = "disabled";
		};

		clock-controller@14410000 {
			compatible = "turbo,trav-clock-gpu";
			reg = < 0x14410000 0x3000 >;
			#clock-cells = < 0x01 >;
			clocks = < 0x18 0x19 0x10 >;
			clock-names = "fin_pll\0dout_cmu_gpu_main_switch";
			status = "okay";
			linux,phandle = < 0x13 >;
			phandle = < 0x13 >;
		};

		clock-controller@12610000 {
			compatible = "turbo,trav-clock-cam_csi";
			reg = < 0x12610000 0x3000 >;
			#clock-cells = < 0x01 >;
			clocks = < 0x18 >;
			clock-names = "fin_pll";
			status = "okay";
		};

		clock-controller@13C10000 {
			compatible = "turbo,trav-clock-trip0";
			reg = < 0x13c10000 0x3000 >;
			#clock-cells = < 0x01 >;
			clocks = < 0x18 0x19 0x10 >;
			clock-names = "fin_pll\0dout_cmu_trip_switchclk";
			status = "okay";
			linux,phandle = < 0xed >;
			phandle = < 0xed >;
		};

		clock-controller@13E10000 {
			compatible = "turbo,trav-clock-trip1";
			reg = < 0x13e10000 0x3000 >;
			#clock-cells = < 0x01 >;
			clocks = < 0x18 0x19 0x10 >;
			clock-names = "fin_pll\0dout_cmu_trip_switchclk";
			status = "okay";
			linux,phandle = < 0xf1 >;
			phandle = < 0xf1 >;
		};

		clock-controller@14C10000 {
			compatible = "turbo,trav-clock-cam_dprx0";
			reg = < 0x14c10000 0x3000 >;
			#clock-cells = < 0x01 >;
			clocks = < 0x18 0x19 0x11 0x19 0x12 >;
			clock-names = "fin_pll\0dout_cmu_dprx_dsc_clk\0dout_cmu_dprx_switchclk";
			status = "disabled";
			linux,phandle = < 0x1d >;
			phandle = < 0x1d >;
		};

		clock-controller@14e10000 {
			compatible = "turbo,trav-clock-cam_dprx1";
			reg = < 0x14e10000 0x3000 >;
			#clock-cells = < 0x01 >;
			clocks = < 0x18 0x19 0x11 0x1d 0x02 0x1d 0x01 >;
			clock-names = "fin_pll\0dout_cmu_dprx_dsc_clk\0mout_cam_dprx0_switch_mux\0mout_cam_dprx0_pll";
			status = "disabled";
			linux,phandle = < 0x88 >;
			phandle = < 0x88 >;
		};

		sysreg_peric@0x14030000 {
			compatible = "samsung,sysreg_peric\0syscon";
			reg = < 0x14030000 0x1000 >;
			linux,phandle = < 0x73 >;
			phandle = < 0x73 >;
		};

		syscon@15030000 {
			compatible = "syscon";
			reg = < 0x15030000 0x1000 >;
			linux,phandle = < 0x6a >;
			phandle = < 0x6a >;
		};

		syscon@16830000 {
			compatible = "syscon";
			reg = < 0x16830000 0x1000 >;
			linux,phandle = < 0xa9 >;
			phandle = < 0xa9 >;
		};

		mct@10040000 {
			compatible = "samsung,exynos4210-mct";
			reg = < 0x10040000 0x800 >;
			interrupts = < 0x00 0x1c7 0x04 0x00 0x1c8 0x04 0x00 0x1c9 0x04 0x00 0x1ca 0x04 0x00 0x1cb 0x04 0x00 0x1cc 0x04 0x00 0x1cd 0x04 0x00 0x1ce 0x04 0x00 0x1cf 0x04 0x00 0x1d0 0x04 0x00 0x1d1 0x04 0x00 0x1d2 0x04 0x00 0x1d3 0x04 0x00 0x1d4 0x04 0x00 0x1d5 0x04 0x00 0x1d6 0x04 >;
			clocks = < 0x18 0x14 0x06 >;
			clock-names = "fin_pll\0mct";
		};

		serial@14180000 {
			compatible = "samsung,exynos4210-uart";
			reg = < 0x14180000 0x100 >;
			interrupts = < 0x00 0xab 0x04 >;
			clocks = < 0x16 0x02 0x16 0x01 >;
			clock-names = "uart\0clk_uart_baud0";
			pinctrl-names = "default";
			pinctrl-0 = < 0x1e >;
			status = "okay";
		};

		serial@14190000 {
			compatible = "samsung,exynos4210-uart";
			reg = < 0x14190000 0x100 >;
			interrupts = < 0x00 0xac 0x04 >;
			clocks = < 0x16 0x04 0x16 0x03 >;
			clock-names = "uart\0clk_uart_baud0";
			pinctrl-names = "default";
			pinctrl-0 = < 0x1f >;
			status = "okay";
		};

		system-controller@11400000 {
			compatible = "samsung,exynos7-pmu\0syscon";
			reg = < 0x11400000 0x5000 >;
			linux,phandle = < 0x20 >;
			phandle = < 0x20 >;
		};

		watchdog@100A0000 {
			compatible = "turbo,trav-wdt";
			reg = < 0x100a0000 0x100 >;
			interrupts = < 0x00 0x1d7 0x00 >;
			samsung,syscon-phandle = < 0x20 >;
			clocks = < 0x18 >;
			clock-names = "watchdog";
			interrupt-mode = < 0x01 >;
		};

		watchdog@100B0000 {
			compatible = "turbo,trav-wdt";
			reg = < 0x100b0000 0x100 >;
			interrupts = < 0x00 0x1d8 0x00 >;
			samsung,syscon-phandle = < 0x20 >;
			clocks = < 0x18 >;
			clock-names = "watchdog";
			interrupt-mode = < 0x01 >;
		};

		watchdog@100C0000 {
			compatible = "turbo,trav-wdt";
			reg = < 0x100c0000 0x100 >;
			interrupts = < 0x00 0x1d9 0x00 >;
			samsung,syscon-phandle = < 0x20 >;
			clocks = < 0x18 >;
			clock-names = "watchdog";
			interrupt-mode = < 0x01 >;
		};

		pwm@14100000 {
			compatible = "samsung,exynos4210-pwm";
			reg = < 0x14100000 0x100 >;
			samsung,pwm-outputs = < 0x00 0x01 0x02 0x03 >;
			#pwm-cells = < 0x03 >;
			clocks = < 0x18 >;
			clock-names = "timers";
			pinctrl-names = "default";
			pinctrl-0 = < 0x21 0x22 0x23 0x24 >;
			status = "okay";
		};

		pwm@14110000 {
			compatible = "samsung,exynos4210-pwm";
			reg = < 0x14110000 0x100 >;
			samsung,pwm-outputs = < 0x00 0x01 0x02 0x03 >;
			#pwm-cells = < 0x03 >;
			clocks = < 0x18 >;
			clock-names = "timers";
			pinctrl-names = "default";
			pinctrl-0 = < 0x25 0x26 0x27 0x28 >;
			status = "okay";
			linux,phandle = < 0xf8 >;
			phandle = < 0xf8 >;
		};

		pinctrl@15020000 {
			compatible = "turbo,trav-pinctrl";
			reg = < 0x15020000 0x1000 >;
			interrupts = < 0x00 0x4f 0x00 >;

			gpf0 {
				gpio-controller;
				#gpio-cells = < 0x02 >;
				interrupt-controller;
				#interrupt-cells = < 0x02 >;
			};

			gpf1 {
				gpio-controller;
				#gpio-cells = < 0x02 >;
				interrupt-controller;
				#interrupt-cells = < 0x02 >;
			};

			gpf6 {
				gpio-controller;
				#gpio-cells = < 0x02 >;
				interrupt-controller;
				#interrupt-cells = < 0x02 >;
			};

			gpf4 {
				gpio-controller;
				#gpio-cells = < 0x02 >;
				interrupt-controller;
				#interrupt-cells = < 0x02 >;
				linux,phandle = < 0xf3 >;
				phandle = < 0xf3 >;
			};

			gpf5 {
				gpio-controller;
				#gpio-cells = < 0x02 >;
				interrupt-controller;
				#interrupt-cells = < 0x02 >;
			};

			usb30-vbus-en {
				samsung,pins = "gpf4-1";
				samsung,pin-function = < 0x01 >;
				samsung,pin-pud = < 0x00 >;
				samsung,pin-drv = < 0x02 >;
				linux,phandle = < 0xf4 >;
				phandle = < 0xf4 >;
			};

			ufs0-rst-n {
				samsung,pins = "gpf5-0";
				samsung,pin-function = < 0x02 >;
				samsung,pin-pud = < 0x00 >;
				samsung,pin-drv = < 0x02 >;
				linux,phandle = < 0x60 >;
				phandle = < 0x60 >;
			};

			ufs0-refclk-out {
				samsung,pins = "gpf5-1";
				samsung,pin-function = < 0x02 >;
				samsung,pin-pud = < 0x00 >;
				samsung,pin-drv = < 0x02 >;
				linux,phandle = < 0x61 >;
				phandle = < 0x61 >;
			};

			ufs0-udpd {
				samsung,pins = "gpf5-2";
				samsung,pin-function = < 0x02 >;
				samsung,pin-pud = < 0x00 >;
				samsung,pin-drv = < 0x02 >;
				linux,phandle = < 0x62 >;
				phandle = < 0x62 >;
			};

			ufs1-rst-n {
				samsung,pins = "gpf5-3";
				samsung,pin-function = < 0x02 >;
				samsung,pin-pud = < 0x00 >;
				samsung,pin-drv = < 0x02 >;
				linux,phandle = < 0x63 >;
				phandle = < 0x63 >;
			};

			ufs1-refclk-out {
				samsung,pins = "gpf5-4";
				samsung,pin-function = < 0x02 >;
				samsung,pin-pud = < 0x00 >;
				samsung,pin-drv = < 0x02 >;
				linux,phandle = < 0x64 >;
				phandle = < 0x64 >;
			};

			ufs1-udpd {
				samsung,pins = "gpf5-5";
				samsung,pin-function = < 0x02 >;
				samsung,pin-pud = < 0x00 >;
				samsung,pin-drv = < 0x02 >;
				linux,phandle = < 0x65 >;
				phandle = < 0x65 >;
			};

			eth0-tx-clk {
				samsung,pins = "gpf0-0";
				samsung,pin-function = < 0x02 >;
				samsung,pin-pud = < 0x01 >;
				samsung,pin-drv = < 0x03 >;
				linux,phandle = < 0x6b >;
				phandle = < 0x6b >;
			};

			eth0-tx-data {
				samsung,pins = "gpf0-1\0gpf0-2\0gpf0-3\0gpf0-4";
				samsung,pin-function = < 0x02 >;
				samsung,pin-pud = < 0x03 >;
				samsung,pin-drv = < 0x03 >;
				linux,phandle = < 0x6c >;
				phandle = < 0x6c >;
			};

			eth0-tx-ctrl {
				samsung,pins = "gpf0-5";
				samsung,pin-function = < 0x02 >;
				samsung,pin-pud = < 0x03 >;
				samsung,pin-drv = < 0x03 >;
				linux,phandle = < 0x6d >;
				phandle = < 0x6d >;
			};

			eth0_phy_intr {
				samsung,pins = "gpf0-6";
				samsung,pin-function = < 0x02 >;
				samsung,pin-pud = < 0x00 >;
				samsung,pin-drv = < 0x02 >;
				linux,phandle = < 0x6e >;
				phandle = < 0x6e >;
			};

			eth0-rx-clk {
				samsung,pins = "gpf1-0";
				samsung,pin-function = < 0x02 >;
				samsung,pin-pud = < 0x03 >;
				samsung,pin-drv = < 0x03 >;
				linux,phandle = < 0x6f >;
				phandle = < 0x6f >;
			};

			eth0-rx-data {
				samsung,pins = "gpf1-1\0gpf1-2\0gpf1-3\0gpf1-4";
				samsung,pin-function = < 0x02 >;
				samsung,pin-pud = < 0x03 >;
				samsung,pin-drv = < 0x03 >;
				linux,phandle = < 0x70 >;
				phandle = < 0x70 >;
			};

			eth0-rx-ctrl {
				samsung,pins = "gpf1-5";
				samsung,pin-function = < 0x02 >;
				samsung,pin-pud = < 0x03 >;
				samsung,pin-drv = < 0x03 >;
				linux,phandle = < 0x71 >;
				phandle = < 0x71 >;
			};

			eth0-mdio {
				samsung,pins = "gpf1-6\0gpf1-7";
				samsung,pin-function = < 0x02 >;
				samsung,pin-pud = < 0x00 >;
				samsung,pin-drv = < 0x02 >;
				linux,phandle = < 0x72 >;
				phandle = < 0x72 >;
			};

			pcie1-clkreq {
				samsung,pins = "gpf6-0";
				samsung,pin-function = < 0x02 >;
				samsung,pin-pud = < 0x03 >;
				samsung,pin-drv = < 0x02 >;
				linux,phandle = < 0xab >;
				phandle = < 0xab >;
			};

			pcie1-wake {
				samsung,pins = "gpf6-1";
				samsung,pin-function = < 0x02 >;
				samsung,pin-pud = < 0x03 >;
				samsung,pin-drv = < 0x02 >;
				linux,phandle = < 0xac >;
				phandle = < 0xac >;
			};

			pcie1-preset {
				samsung,pins = "gpf6-2";
				samsung,pin-function = < 0x02 >;
				samsung,pin-pud = < 0x03 >;
				samsung,pin-drv = < 0x02 >;
				linux,phandle = < 0xad >;
				phandle = < 0xad >;
			};
		};

		pinctrl@141F0000 {
			compatible = "turbo,trav-pinctrl";
			reg = < 0x141f0000 0x1000 >;
			interrupts = < 0x00 0xbd 0x00 >;

			gpc8 {
				gpio-controller;
				#gpio-cells = < 0x02 >;
				interrupt-controller;
				#interrupt-cells = < 0x02 >;
			};

			gpf2 {
				gpio-controller;
				#gpio-cells = < 0x02 >;
				interrupt-controller;
				#interrupt-cells = < 0x02 >;
			};

			gpf3 {
				gpio-controller;
				#gpio-cells = < 0x02 >;
				interrupt-controller;
				#interrupt-cells = < 0x02 >;
			};

			gpd0 {
				gpio-controller;
				#gpio-cells = < 0x02 >;
				interrupt-controller;
				#interrupt-cells = < 0x02 >;
			};

			gpb0 {
				gpio-controller;
				#gpio-cells = < 0x02 >;
				interrupt-controller;
				#interrupt-cells = < 0x02 >;
			};

			gpb1 {
				gpio-controller;
				#gpio-cells = < 0x02 >;
				interrupt-controller;
				#interrupt-cells = < 0x02 >;
			};

			gpb4 {
				gpio-controller;
				#gpio-cells = < 0x02 >;
				interrupt-controller;
				#interrupt-cells = < 0x02 >;
				linux,phandle = < 0x2c >;
				phandle = < 0x2c >;
			};

			gpb5 {
				gpio-controller;
				#gpio-cells = < 0x02 >;
				interrupt-controller;
				#interrupt-cells = < 0x02 >;
			};

			gpb6 {
				gpio-controller;
				#gpio-cells = < 0x02 >;
				interrupt-controller;
				#interrupt-cells = < 0x02 >;
			};

			gpb7 {
				gpio-controller;
				#gpio-cells = < 0x02 >;
				interrupt-controller;
				#interrupt-cells = < 0x02 >;
			};

			gpd1 {
				gpio-controller;
				#gpio-cells = < 0x02 >;
				interrupt-controller;
				#interrupt-cells = < 0x02 >;
			};

			gpd2 {
				gpio-controller;
				#gpio-cells = < 0x02 >;
				interrupt-controller;
				#interrupt-cells = < 0x02 >;
			};

			gpd3 {
				gpio-controller;
				#gpio-cells = < 0x02 >;
				interrupt-controller;
				#interrupt-cells = < 0x02 >;
			};

			gpg0 {
				gpio-controller;
				#gpio-cells = < 0x02 >;
				interrupt-controller;
				#interrupt-cells = < 0x02 >;
				linux,phandle = < 0x2d >;
				phandle = < 0x2d >;
			};

			gpg1 {
				gpio-controller;
				#gpio-cells = < 0x02 >;
				interrupt-controller;
				#interrupt-cells = < 0x02 >;
				linux,phandle = < 0x59 >;
				phandle = < 0x59 >;
			};

			gpg2 {
				gpio-controller;
				#gpio-cells = < 0x02 >;
				interrupt-controller;
				#interrupt-cells = < 0x02 >;
				linux,phandle = < 0xf5 >;
				phandle = < 0xf5 >;
			};

			gpg3 {
				gpio-controller;
				#gpio-cells = < 0x02 >;
				interrupt-controller;
				#interrupt-cells = < 0x02 >;
			};

			gpg4 {
				gpio-controller;
				#gpio-cells = < 0x02 >;
				interrupt-controller;
				#interrupt-cells = < 0x02 >;
			};

			gpg5 {
				gpio-controller;
				#gpio-cells = < 0x02 >;
				interrupt-controller;
				#interrupt-cells = < 0x02 >;
			};

			gpg6 {
				gpio-controller;
				#gpio-cells = < 0x02 >;
				interrupt-controller;
				#interrupt-cells = < 0x02 >;
			};

			gpg7 {
				gpio-controller;
				#gpio-cells = < 0x02 >;
				interrupt-controller;
				#interrupt-cells = < 0x02 >;
			};

			spi0-bus {
				samsung,pins = "gpb4-0\0gpb4-2\0gpb4-3";
				samsung,pin-function = < 0x02 >;
				samsung,pin-pud = < 0x03 >;
				samsung,pin-drv = < 0x00 >;
				linux,phandle = < 0x2a >;
				phandle = < 0x2a >;
			};

			spi1-bus {
				samsung,pins = "gpb4-4\0gpb4-6\0gpb4-7";
				samsung,pin-function = < 0x02 >;
				samsung,pin-pud = < 0x03 >;
				samsung,pin-drv = < 0x00 >;
				linux,phandle = < 0x2b >;
				phandle = < 0x2b >;
			};

			spi2-bus {
				samsung,pins = "gpb5-0\0gpb5-2\0gpb5-3";
				samsung,pin-function = < 0x02 >;
				samsung,pin-pud = < 0x03 >;
				samsung,pin-drv = < 0x00 >;
				linux,phandle = < 0x2e >;
				phandle = < 0x2e >;
			};

			pwm0-out0 {
				samsung,pins = "gpb6-0";
				samsung,pin-function = < 0x02 >;
				samsung,pin-pud = < 0x03 >;
				samsung,pin-drv = < 0x02 >;
				linux,phandle = < 0x21 >;
				phandle = < 0x21 >;
			};

			pwm0-out1 {
				samsung,pins = "gpb6-1";
				samsung,pin-function = < 0x02 >;
				samsung,pin-pud = < 0x03 >;
				samsung,pin-drv = < 0x02 >;
				linux,phandle = < 0x22 >;
				phandle = < 0x22 >;
			};

			pwm0-out2 {
				samsung,pins = "gpb6-2";
				samsung,pin-function = < 0x02 >;
				samsung,pin-pud = < 0x03 >;
				samsung,pin-drv = < 0x02 >;
				linux,phandle = < 0x23 >;
				phandle = < 0x23 >;
			};

			pwm0-out3 {
				samsung,pins = "gpb6-3";
				samsung,pin-function = < 0x02 >;
				samsung,pin-pud = < 0x03 >;
				samsung,pin-drv = < 0x02 >;
				linux,phandle = < 0x24 >;
				phandle = < 0x24 >;
			};

			pwm1-out0 {
				samsung,pins = "gpb6-4";
				samsung,pin-function = < 0x02 >;
				samsung,pin-pud = < 0x03 >;
				samsung,pin-drv = < 0x02 >;
				linux,phandle = < 0x25 >;
				phandle = < 0x25 >;
			};

			pwm1-out1 {
				samsung,pins = "gpb6-5";
				samsung,pin-function = < 0x02 >;
				samsung,pin-pud = < 0x03 >;
				samsung,pin-drv = < 0x02 >;
				linux,phandle = < 0x26 >;
				phandle = < 0x26 >;
			};

			pwm1-out2 {
				samsung,pins = "gpb6-6";
				samsung,pin-function = < 0x02 >;
				samsung,pin-pud = < 0x03 >;
				samsung,pin-drv = < 0x02 >;
				linux,phandle = < 0x27 >;
				phandle = < 0x27 >;
			};

			pwm1-out3 {
				samsung,pins = "gpb6-7";
				samsung,pin-function = < 0x02 >;
				samsung,pin-pud = < 0x03 >;
				samsung,pin-drv = < 0x02 >;
				linux,phandle = < 0x28 >;
				phandle = < 0x28 >;
			};

			uart0-data {
				samsung,pins = "gpb7-0\0gpb7-1";
				samsung,pin-function = < 0x02 >;
				samsung,pin-pud = < 0x00 >;
				samsung,pin-drv = < 0x00 >;
				linux,phandle = < 0x1e >;
				phandle = < 0x1e >;
			};

			uart1-data {
				samsung,pins = "gpb7-4\0gpb7-5";
				samsung,pin-function = < 0x02 >;
				samsung,pin-pud = < 0x00 >;
				samsung,pin-drv = < 0x00 >;
				linux,phandle = < 0x1f >;
				phandle = < 0x1f >;
			};

			hs-i2c0-bus {
				samsung,pins = "gpb0-0\0gpb0-1";
				samsung,pin-function = < 0x02 >;
				samsung,pin-pud = < 0x03 >;
				samsung,pin-drv = < 0x00 >;
				linux,phandle = < 0x2f >;
				phandle = < 0x2f >;
			};

			hs-i2c1-bus {
				samsung,pins = "gpb0-2\0gpb0-3";
				samsung,pin-function = < 0x02 >;
				samsung,pin-pud = < 0x03 >;
				samsung,pin-drv = < 0x00 >;
				linux,phandle = < 0x3c >;
				phandle = < 0x3c >;
			};

			hs-i2c2-bus {
				samsung,pins = "gpb0-4\0gpb0-5";
				samsung,pin-function = < 0x02 >;
				samsung,pin-pud = < 0x03 >;
				samsung,pin-drv = < 0x00 >;
				linux,phandle = < 0x55 >;
				phandle = < 0x55 >;
			};

			hs-i2c3-bus {
				samsung,pins = "gpb0-6\0gpb0-7";
				samsung,pin-function = < 0x02 >;
				samsung,pin-pud = < 0x03 >;
				samsung,pin-drv = < 0x00 >;
				linux,phandle = < 0x56 >;
				phandle = < 0x56 >;
			};

			hs-i2c4-bus {
				samsung,pins = "gpb1-0\0gpb1-1";
				samsung,pin-function = < 0x02 >;
				samsung,pin-pud = < 0x03 >;
				samsung,pin-drv = < 0x00 >;
				linux,phandle = < 0x57 >;
				phandle = < 0x57 >;
			};

			hs-i2c5-bus {
				samsung,pins = "gpb1-2\0gpb1-3";
				samsung,pin-function = < 0x02 >;
				samsung,pin-pud = < 0x03 >;
				samsung,pin-drv = < 0x00 >;
				linux,phandle = < 0x58 >;
				phandle = < 0x58 >;
			};

			hs-i2c6-bus {
				samsung,pins = "gpb1-4\0gpb1-5";
				samsung,pin-function = < 0x02 >;
				samsung,pin-pud = < 0x03 >;
				samsung,pin-drv = < 0x00 >;
				linux,phandle = < 0x5a >;
				phandle = < 0x5a >;
			};

			hs-i2c7-bus {
				samsung,pins = "gpb1-6\0gpb1-7";
				samsung,pin-function = < 0x02 >;
				samsung,pin-pud = < 0x03 >;
				samsung,pin-drv = < 0x00 >;
				linux,phandle = < 0x5b >;
				phandle = < 0x5b >;
			};

			eth1-tx-clk {
				samsung,pins = "gpf2-0";
				samsung,pin-function = < 0x02 >;
				samsung,pin-pud = < 0x01 >;
				samsung,pin-drv = < 0x03 >;
				linux,phandle = < 0x74 >;
				phandle = < 0x74 >;
			};

			eth1-tx-data {
				samsung,pins = "gpf2-1\0gpf2-2\0gpf2-3\0gpf2-4";
				samsung,pin-function = < 0x02 >;
				samsung,pin-pud = < 0x03 >;
				samsung,pin-drv = < 0x03 >;
				linux,phandle = < 0x75 >;
				phandle = < 0x75 >;
			};

			eth1-tx-ctrl {
				samsung,pins = "gpf2-5";
				samsung,pin-function = < 0x02 >;
				samsung,pin-pud = < 0x03 >;
				samsung,pin-drv = < 0x03 >;
				linux,phandle = < 0x76 >;
				phandle = < 0x76 >;
			};

			eth1_phy_intr {
				samsung,pins = "gpf2-6";
				samsung,pin-function = < 0x02 >;
				samsung,pin-pud = < 0x03 >;
				samsung,pin-drv = < 0x02 >;
				linux,phandle = < 0x77 >;
				phandle = < 0x77 >;
			};

			eth1-rx-clk {
				samsung,pins = "gpf3-0";
				samsung,pin-function = < 0x02 >;
				samsung,pin-pud = < 0x03 >;
				samsung,pin-drv = < 0x03 >;
				linux,phandle = < 0x78 >;
				phandle = < 0x78 >;
			};

			eth1-rx-data {
				samsung,pins = "gpf3-1\0gpf3-2\0gpf3-3\0gpf3-4";
				samsung,pin-function = < 0x02 >;
				samsung,pin-pud = < 0x03 >;
				samsung,pin-drv = < 0x03 >;
				linux,phandle = < 0x79 >;
				phandle = < 0x79 >;
			};

			eth1-rx-ctrl {
				samsung,pins = "gpf3-5";
				samsung,pin-function = < 0x02 >;
				samsung,pin-pud = < 0x03 >;
				samsung,pin-drv = < 0x03 >;
				linux,phandle = < 0x7a >;
				phandle = < 0x7a >;
			};

			eth1-mdio {
				samsung,pins = "gpf3-6\0gpf3-7";
				samsung,pin-function = < 0x02 >;
				samsung,pin-pud = < 0x03 >;
				samsung,pin-drv = < 0x02 >;
				linux,phandle = < 0x7b >;
				phandle = < 0x7b >;
			};

			pcie0-clkreq {
				samsung,pins = "gpc8-0";
				samsung,pin-function = < 0x02 >;
				samsung,pin-pud = < 0x03 >;
				samsung,pin-drv = < 0x02 >;
				linux,phandle = < 0xb0 >;
				phandle = < 0xb0 >;
			};

			pcie0-wake1 {
				samsung,pins = "gpc8-3";
				samsung,pin-function = < 0x02 >;
				samsung,pin-pud = < 0x03 >;
				samsung,pin-drv = < 0x02 >;
				linux,phandle = < 0xb3 >;
				phandle = < 0xb3 >;
			};

			pcie0-wake0 {
				samsung,pins = "gpc8-1";
				samsung,pin-function = < 0x02 >;
				samsung,pin-pud = < 0x03 >;
				samsung,pin-drv = < 0x02 >;
				linux,phandle = < 0xb1 >;
				phandle = < 0xb1 >;
			};

			pcie0-preset0 {
				samsung,pins = "gpc8-2";
				samsung,pin-function = < 0x02 >;
				samsung,pin-pud = < 0x03 >;
				samsung,pin-drv = < 0x02 >;
				linux,phandle = < 0xb2 >;
				phandle = < 0xb2 >;
			};

			m_can0-bus {
				samsung,pins = "gpd0-0\0gpd0-1";
				samsung,pin-function = < 0x02 >;
				samsung,pin-pud = < 0x03 >;
				samsung,pin-drv = < 0x00 >;
				linux,phandle = < 0xb4 >;
				phandle = < 0xb4 >;
			};

			m_can1-bus {
				samsung,pins = "gpd0-2\0gpd0-3";
				samsung,pin-function = < 0x02 >;
				samsung,pin-pud = < 0x03 >;
				samsung,pin-drv = < 0x00 >;
				linux,phandle = < 0xb5 >;
				phandle = < 0xb5 >;
			};

			m_can2-bus {
				samsung,pins = "gpd0-4\0gpd0-5";
				samsung,pin-function = < 0x02 >;
				samsung,pin-pud = < 0x03 >;
				samsung,pin-drv = < 0x00 >;
				linux,phandle = < 0xb6 >;
				phandle = < 0xb6 >;
			};

			m_can3-bus {
				samsung,pins = "gpd0-6\0gpd0-7";
				samsung,pin-function = < 0x02 >;
				samsung,pin-pud = < 0x03 >;
				samsung,pin-drv = < 0x00 >;
				linux,phandle = < 0xb7 >;
				phandle = < 0xb7 >;
			};

			i2s0-bus {
				samsung,pins = "gpd1-0\0gpd1-1\0gpd1-2\0gpd1-3\0gpd1-4";
				samsung,pin-function = < 0x02 >;
				samsung,pin-pud = < 0x01 >;
				samsung,pin-drv = < 0x00 >;
				linux,phandle = < 0xeb >;
				phandle = < 0xeb >;
			};
		};

		pinctrl@114F0000 {
			compatible = "turbo,trav-pinctrl";
			reg = < 0x114f0000 0x1000 >;

			gpq0 {
				gpio-controller;
				#gpio-cells = < 0x02 >;
			};
		};

		spi@14140000 {
			compatible = "turbo,trav-spi";
			reg = < 0x14140000 0x100 >;
			interrupts = < 0x00 0x9c 0x04 >;
			dmas = < 0x29 0x04 0x29 0x05 >;
			dma-names = "tx\0rx";
			#address-cells = < 0x01 >;
			#size-cells = < 0x00 >;
			clocks = < 0x16 0x09 0x16 0x0a >;
			clock-names = "spi\0spi_busclk0";
			samsung,spi-src-clk = < 0x00 >;
			pinctrl-names = "default";
			pinctrl-0 = < 0x2a >;
			num-cs = < 0x01 >;
			status = "okay";
		};

		spi@14150000 {
			compatible = "turbo,trav-spi";
			reg = < 0x14150000 0x100 >;
			interrupts = < 0x00 0x9d 0x04 >;
			dmas = < 0x29 0x06 0x29 0x07 >;
			dma-names = "tx\0rx";
			#address-cells = < 0x01 >;
			#size-cells = < 0x00 >;
			clocks = < 0x16 0x0b 0x16 0x0c >;
			clock-names = "spi\0spi_busclk0";
			samsung,spi-src-clk = < 0x00 >;
			pinctrl-names = "default";
			pinctrl-0 = < 0x2b >;
			num-cs = < 0x02 >;
			status = "okay";
			cs-gpios = < 0x2c 0x05 0x01 0x2d 0x06 0x01 >;

			spi@0 {
				compatible = "smi130_accel";
				spi-max-frequency = < 0xf4240 >;
				reg = < 0x00 >;

				controller-data {
					samsung,spi-feedback-delay = < 0x00 >;
				};
			};

			spi@1 {
				compatible = "bmg160";
				spi-max-frequency = < 0xf4240 >;
				reg = < 0x01 >;

				controller-data {
					samsung,spi-feedback-delay = < 0x00 >;
				};
			};
		};

		spi@14160000 {
			compatible = "turbo,trav-spi";
			reg = < 0x14160000 0x100 >;
			interrupts = < 0x00 0x9e 0x04 >;
			dmas = < 0x29 0x08 0x29 0x09 >;
			dma-names = "tx\0rx";
			#address-cells = < 0x01 >;
			#size-cells = < 0x00 >;
			clocks = < 0x16 0x0d 0x16 0x0e >;
			clock-names = "spi\0spi_busclk0";
			samsung,spi-src-clk = < 0x00 >;
			pinctrl-names = "default";
			pinctrl-0 = < 0x2e >;
			num-cs = < 0x01 >;
			status = "okay";
		};

		hsi2c@14200000 {
			compatible = "samsung,exynos7-hsi2c";
			reg = < 0x14200000 0x1000 >;
			interrupts = < 0x00 0x94 0x00 >;
			#address-cells = < 0x01 >;
			#size-cells = < 0x00 >;
			pinctrl-names = "default";
			pinctrl-0 = < 0x2f >;
			clocks = < 0x16 0x10 >;
			clock-names = "hsi2c";
			status = "okay";

			dummysensor1@0x10 {
				compatible = "turbo,trav-sensor0";
				reg = < 0x10 >;

				port {
					#address-cells = < 0x01 >;
					#size-cells = < 0x00 >;

					endpoint {
						reg = < 0x00 >;
						clock-lanes = < 0x00 >;
						data-lanes = < 0x01 0x02 0x03 0x04 >;
						remote-endpoint = < 0x30 >;
						linux,phandle = < 0x7c >;
						phandle = < 0x7c >;
					};
				};
			};

			dummysensor2@0x11 {
				compatible = "turbo,trav-sensor1";
				reg = < 0x11 >;

				port {
					#address-cells = < 0x01 >;
					#size-cells = < 0x00 >;

					endpoint {
						reg = < 0x00 >;
						clock-lanes = < 0x00 >;
						data-lanes = < 0x01 0x02 0x03 0x04 >;
						remote-endpoint = < 0x31 >;
						linux,phandle = < 0x7d >;
						phandle = < 0x7d >;
					};
				};
			};

			dummysensor3@0x12 {
				compatible = "turbo,trav-sensor2";
				reg = < 0x12 >;

				port {
					#address-cells = < 0x01 >;
					#size-cells = < 0x00 >;

					endpoint {
						reg = < 0x00 >;
						clock-lanes = < 0x00 >;
						data-lanes = < 0x01 0x02 0x03 0x04 >;
						remote-endpoint = < 0x32 >;
						linux,phandle = < 0x7e >;
						phandle = < 0x7e >;
					};
				};
			};

			dummysensor4@0x13 {
				compatible = "turbo,trav-sensor3";
				reg = < 0x13 >;

				port {
					#address-cells = < 0x01 >;
					#size-cells = < 0x00 >;

					endpoint {
						reg = < 0x00 >;
						clock-lanes = < 0x00 >;
						data-lanes = < 0x01 0x02 0x03 0x04 >;
						remote-endpoint = < 0x33 >;
						linux,phandle = < 0x7f >;
						phandle = < 0x7f >;
					};
				};
			};

			dummysensor5@0x14 {
				compatible = "turbo,trav-sensor4";
				reg = < 0x14 >;

				port {
					#address-cells = < 0x01 >;
					#size-cells = < 0x00 >;

					endpoint {
						reg = < 0x00 >;
						clock-lanes = < 0x00 >;
						data-lanes = < 0x01 0x02 0x03 0x04 >;
						remote-endpoint = < 0x34 >;
						linux,phandle = < 0x80 >;
						phandle = < 0x80 >;
					};
				};
			};

			dummysensor6@0x15 {
				compatible = "turbo,trav-sensor5";
				reg = < 0x15 >;

					port {
					#address-cells = < 0x01 >;
					#size-cells = < 0x00 >;

					endpoint {
						reg = < 0x00 >;
						clock-lanes = < 0x00 >;
						data-lanes = < 0x01 0x02 0x03 0x04 >;
						remote-endpoint = < 0x35 >;
						linux,phandle = < 0x81 >;
						phandle = < 0x81 >;
					};
				};
			};

			dummysensor7@0x16 {
				compatible = "turbo,trav-sensor6";
				reg = < 0x16 >;

				port {
					#address-cells = < 0x01 >;
					#size-cells = < 0x00 >;

					endpoint {
						reg = < 0x00 >;
						clock-lanes = < 0x00 >;
						data-lanes = < 0x01 0x02 0x03 0x04 >;
						remote-endpoint = < 0x36 >;
						linux,phandle = < 0x82 >;
						phandle = < 0x82 >;
					};
				};
			};

			dummysensor8@0x17 {
				compatible = "turbo,trav-sensor7";
				reg = < 0x17 >;

				port {
					#address-cells = < 0x01 >;
					#size-cells = < 0x00 >;

					endpoint {
						reg = < 0x00 >;
						clock-lanes = < 0x00 >;
						data-lanes = < 0x01 0x02 0x03 0x04 >;
						remote-endpoint = < 0x37 >;
						linux,phandle = < 0x83 >;
						phandle = < 0x83 >;
					};
				};
			};

			dummysensor9@0x18 {
				compatible = "turbo,trav-sensor8";
				reg = < 0x18 >;

				port {
					#address-cells = < 0x01 >;
					#size-cells = < 0x00 >;

					endpoint {
						reg = < 0x00 >;
						clock-lanes = < 0x00 >;
						data-lanes = < 0x01 0x02 >;
						remote-endpoint = < 0x38 >;
						linux,phandle = < 0x84 >;
						phandle = < 0x84 >;
					};
				};
			};

			dummysensor10@0x19 {
				compatible = "turbo,trav-sensor9";
				reg = < 0x19 >;

				port {
					#address-cells = < 0x01 >;
					#size-cells = < 0x00 >;

					endpoint {
						reg = < 0x00 >;
						clock-lanes = < 0x00 >;
						data-lanes = < 0x01 0x02 >;
						remote-endpoint = < 0x39 >;
						linux,phandle = < 0x85 >;
						phandle = < 0x85 >;
					};
				};
			};

			dummysensor11@0x1A {
				compatible = "turbo,trav-sensor10";
				reg = < 0x1a >;

				port {
					#address-cells = < 0x01 >;
					#size-cells = < 0x00 >;

					endpoint {
						reg = < 0x00 >;
						clock-lanes = < 0x00 >;
						data-lanes = < 0x01 0x02 >;
						remote-endpoint = < 0x3a >;
						linux,phandle = < 0x86 >;
						phandle = < 0x86 >;
					};
				};
			};

			dummysensor12@0x1B {
				compatible = "turbo,trav-sensor11";
				reg = < 0x1b >;

				port {
					#address-cells = < 0x01 >;
					#size-cells = < 0x00 >;

					endpoint {
						reg = < 0x00 >;
						clock-lanes = < 0x00 >;
						data-lanes = < 0x01 0x02 >;
						remote-endpoint = < 0x3b >;
						linux,phandle = < 0x87 >;
						phandle = < 0x87 >;
					};
				};
			};
		};

		hsi2c@14210000 {
			compatible = "samsung,exynos7-hsi2c";
			reg = < 0x14210000 0x1000 >;
			interrupts = < 0x00 0x95 0x00 >;
			#address-cells = < 0x01 >;
			#size-cells = < 0x00 >;
			pinctrl-names = "default";
			pinctrl-0 = < 0x3c >;
			clocks = < 0x16 0x11 >;
			clock-names = "hsi2c";
			status = "okay";

			dummy_sensor@10 {
				compatible = "trav-sensor0";
				reg = < 0x10 >;

				port {
					#address-cells = < 0x01 >;
					#size-cells = < 0x00 >;

					endpoint {
						reg = < 0x00 >;
						clock-lanes = < 0x00 >;
						data-lanes = < 0x01 0x02 0x03 0x04 >;
						remote-endpoint = < 0x3d >;
						linux,phandle = < 0x89 >;
						phandle = < 0x89 >;
					};
				};
			};

			dummy_sensor@11 {
				compatible = "trav-sensor0";
				reg = < 0x11 >;

				port {
					#address-cells = < 0x01 >;
					#size-cells = < 0x00 >;

					endpoint {
						reg = < 0x01 >;
						clock-lanes = < 0x00 >;
						data-lanes = < 0x01 0x02 0x03 0x04 >;
						remote-endpoint = < 0x3e >;
						linux,phandle = < 0x8a >;
						phandle = < 0x8a >;
					};
				};
			};

			dummy_sensor@12 {
				compatible = "trav-sensor0";
				reg = < 0x12 >;

				port {
					#address-cells = < 0x01 >;
					#size-cells = < 0x00 >;

					endpoint {
						reg = < 0x02 >;
						clock-lanes = < 0x00 >;
						data-lanes = < 0x01 0x02 0x03 0x04 >;
						remote-endpoint = < 0x3f >;
						linux,phandle = < 0x8b >;
						phandle = < 0x8b >;
					};
				};
			};

			dummy_sensor@13 {
				compatible = "trav-sensor0";
				reg = < 0x13 >;

				port {
					#address-cells = < 0x01 >;
					#size-cells = < 0x00 >;

					endpoint {
						reg = < 0x03 >;
						clock-lanes = < 0x00 >;
						data-lanes = < 0x01 0x02 0x03 0x04 >;
						remote-endpoint = < 0x40 >;
						linux,phandle = < 0x8c >;
						phandle = < 0x8c >;
					};
				};
			};

			dummy_sensor@14 {
				compatible = "trav-sensor0";
				reg = < 0x14 >;

				port {
					#address-cells = < 0x01 >;
					#size-cells = < 0x00 >;

					endpoint {
						reg = < 0x04 >;
						clock-lanes = < 0x00 >;
						data-lanes = < 0x01 0x02 0x03 0x04 >;
						remote-endpoint = < 0x41 >;
						linux,phandle = < 0x8d >;
						phandle = < 0x8d >;
					};
				};
			};

			dummy_sensor@15 {
				compatible = "trav-sensor0";
				reg = < 0x15 >;

				port {
					#address-cells = < 0x01 >;
					#size-cells = < 0x00 >;

					endpoint {
						reg = < 0x05 >;
						clock-lanes = < 0x00 >;
						data-lanes = < 0x01 0x02 0x03 0x04 >;
						remote-endpoint = < 0x42 >;
						linux,phandle = < 0x8e >;
						phandle = < 0x8e >;
					};
				};
			};

			dummy_sensor@16 {
				compatible = "trav-sensor0";
				reg = < 0x16 >;

				port {
					#address-cells = < 0x01 >;
					#size-cells = < 0x00 >;

					endpoint {
						reg = < 0x06 >;
						clock-lanes = < 0x00 >;
						data-lanes = < 0x01 0x02 0x03 0x04 >;
						remote-endpoint = < 0x43 >;
						linux,phandle = < 0x8f >;
						phandle = < 0x8f >;
					};
				};
			};

			dummy_sensor@17 {
				compatible = "trav-sensor0";
				reg = < 0x17 >;

				port {
					#address-cells = < 0x01 >;
					#size-cells = < 0x00 >;

					endpoint {
						reg = < 0x07 >;
						clock-lanes = < 0x00 >;
						data-lanes = < 0x01 0x02 0x03 0x04 >;
						remote-endpoint = < 0x44 >;
						linux,phandle = < 0x90 >;
						phandle = < 0x90 >;
					};
				};
			};

			dummy_sensor@20 {
				compatible = "trav-sensor1";
				reg = < 0x20 >;

				port {
					#address-cells = < 0x01 >;
					#size-cells = < 0x00 >;

					endpoint {
						reg = < 0x00 >;
						clock-lanes = < 0x00 >;
						data-lanes = < 0x01 0x02 0x03 0x04 >;
						remote-endpoint = < 0x45 >;
						linux,phandle = < 0x91 >;
						phandle = < 0x91 >;
					};
				};
			};

			dummy_sensor@21 {
				compatible = "trav-sensor1";
				reg = < 0x21 >;

				port {
					#address-cells = < 0x01 >;
					#size-cells = < 0x00 >;

					endpoint {
						reg = < 0x01 >;
						clock-lanes = < 0x00 >;
						data-lanes = < 0x01 0x02 0x03 0x04 >;
						remote-endpoint = < 0x46 >;
						linux,phandle = < 0x92 >;
						phandle = < 0x92 >;
					};
				};
			};

			dummy_sensor@22 {
				compatible = "trav-sensor1";
				reg = < 0x22 >;

				port {
					#address-cells = < 0x01 >;
					#size-cells = < 0x00 >;

					endpoint {
						reg = < 0x02 >;
						clock-lanes = < 0x00 >;
						data-lanes = < 0x01 0x02 0x03 0x04 >;
						remote-endpoint = < 0x47 >;
						linux,phandle = < 0x93 >;
						phandle = < 0x93 >;
					};
				};
			};

			dummy_sensor@23 {
				compatible = "trav-sensor1";
				reg = < 0x23 >;

				port {
					#address-cells = < 0x01 >;
					#size-cells = < 0x00 >;

					endpoint {
						reg = < 0x03 >;
						clock-lanes = < 0x00 >;
						data-lanes = < 0x01 0x02 0x03 0x04 >;
						remote-endpoint = < 0x48 >;
						linux,phandle = < 0x94 >;
						phandle = < 0x94 >;
					};
				};
			};

			dummy_sensor@24 {
				compatible = "trav-sensor1";
				reg = < 0x24 >;

				port {
					#address-cells = < 0x01 >;
					#size-cells = < 0x00 >;

					endpoint {
						reg = < 0x04 >;
						clock-lanes = < 0x00 >;
						data-lanes = < 0x01 0x02 0x03 0x04 >;
						remote-endpoint = < 0x49 >;
						linux,phandle = < 0x95 >;
						phandle = < 0x95 >;
					};
				};
			};

			dummy_sensor@25 {
				compatible = "trav-sensor1";
				reg = < 0x25 >;

				port {
					#address-cells = < 0x01 >;
					#size-cells = < 0x00 >;

					endpoint {
						reg = < 0x05 >;
						clock-lanes = < 0x00 >;
						data-lanes = < 0x01 0x02 0x03 0x04 >;
						remote-endpoint = < 0x4a >;
						linux,phandle = < 0x96 >;
						phandle = < 0x96 >;
					};
				};
			};

			dummy_sensor@26 {
				compatible = "trav-sensor1";
				reg = < 0x26 >;

				port {
					#address-cells = < 0x01 >;
					#size-cells = < 0x00 >;

					endpoint {
						reg = < 0x06 >;
						clock-lanes = < 0x00 >;
						data-lanes = < 0x01 0x02 0x03 0x04 >;
						remote-endpoint = < 0x4b >;
						linux,phandle = < 0x97 >;
						phandle = < 0x97 >;
					};
				};
			};

			dummy_sensor@27 {
				compatible = "trav-sensor1";
				reg = < 0x27 >;

				port {
					#address-cells = < 0x01 >;
					#size-cells = < 0x00 >;

					endpoint {
						reg = < 0x07 >;
						clock-lanes = < 0x00 >;
						data-lanes = < 0x01 0x02 0x03 0x04 >;
						remote-endpoint = < 0x4c >;
						linux,phandle = < 0x98 >;
						phandle = < 0x98 >;
					};
				};
			};

			dummy_sensor@30 {
				compatible = "trav-sensor2";
				reg = < 0x30 >;

				port {
					#address-cells = < 0x01 >;
					#size-cells = < 0x00 >;

					endpoint {
						reg = < 0x00 >;
						clock-lanes = < 0x00 >;
						data-lanes = < 0x01 0x02 0x03 0x04 >;
						remote-endpoint = < 0x4d >;
						linux,phandle = < 0x99 >;
						phandle = < 0x99 >;
					};
				};
			};

			dummy_sensor@31 {
				compatible = "trav-sensor2";
				reg = < 0x31 >;

				port {
					#address-cells = < 0x01 >;
					#size-cells = < 0x00 >;

					endpoint {
						reg = < 0x01 >;
						clock-lanes = < 0x00 >;
						data-lanes = < 0x01 0x02 0x03 0x04 >;
						remote-endpoint = < 0x4e >;
						linux,phandle = < 0x9a >;
						phandle = < 0x9a >;
					};
				};
			};

			dummy_sensor@32 {
				compatible = "trav-sensor2";
				reg = < 0x32 >;

				port {
					#address-cells = < 0x01 >;
					#size-cells = < 0x00 >;

					endpoint {
						reg = < 0x02 >;
						clock-lanes = < 0x00 >;
						data-lanes = < 0x01 0x02 0x03 0x04 >;
						remote-endpoint = < 0x4f >;
						linux,phandle = < 0x9b >;
						phandle = < 0x9b >;
					};
				};
			};

			dummy_sensor@33 {
				compatible = "trav-sensor2";
				reg = < 0x33 >;

				port {
					#address-cells = < 0x01 >;
					#size-cells = < 0x00 >;

					endpoint {
						reg = < 0x03 >;
						clock-lanes = < 0x00 >;
						data-lanes = < 0x01 0x02 0x03 0x04 >;
						remote-endpoint = < 0x50 >;
						linux,phandle = < 0x9c >;
						phandle = < 0x9c >;
					};
				};
			};

			dummy_sensor@34 {
				compatible = "trav-sensor2";
				reg = < 0x34 >;

				port {
					#address-cells = < 0x01 >;
					#size-cells = < 0x00 >;

					endpoint {
						reg = < 0x04 >;
						clock-lanes = < 0x00 >;
						data-lanes = < 0x01 0x02 0x03 0x04 >;
						remote-endpoint = < 0x51 >;
						linux,phandle = < 0x9d >;
						phandle = < 0x9d >;
					};
				};
			};

			dummy_sensor@35 {
				compatible = "trav-sensor2";
				reg = < 0x35 >;

				port {
					#address-cells = < 0x01 >;
					#size-cells = < 0x00 >;

					endpoint {
						reg = < 0x05 >;
						clock-lanes = < 0x00 >;
						data-lanes = < 0x01 0x02 0x03 0x04 >;
						remote-endpoint = < 0x52 >;
						linux,phandle = < 0x9e >;
						phandle = < 0x9e >;
					};
				};
			};

			dummy_sensor@36 {
				compatible = "trav-sensor2";
				reg = < 0x36 >;

				port {
					#address-cells = < 0x01 >;
					#size-cells = < 0x00 >;

					endpoint {
						reg = < 0x06 >;
						clock-lanes = < 0x00 >;
						data-lanes = < 0x01 0x02 0x03 0x04 >;
						remote-endpoint = < 0x53 >;
						linux,phandle = < 0x9f >;
						phandle = < 0x9f >;
					};
				};
			};

			dummy_sensor@37 {
				compatible = "trav-sensor2";
				reg = < 0x37 >;

				port {
					#address-cells = < 0x01 >;
					#size-cells = < 0x00 >;

					endpoint {
						reg = < 0x07 >;
						clock-lanes = < 0x00 >;
						data-lanes = < 0x01 0x02 0x03 0x04 >;
						remote-endpoint = < 0x54 >;
						linux,phandle = < 0xa0 >;
						phandle = < 0xa0 >;
					};
				};
			};

			dummy_sensor@40 {
				compatible = "trav-sensor3";
				reg = < 0x40 >;

				port {
					#address-cells = < 0x01 >;
					#size-cells = < 0x00 >;

					endpoint {
						reg = < 0x00 >;
						clock-lanes = < 0x00 >;
						data-lanes = < 0x01 0x02 0x03 0x04 >;
						remote-endpoint = < 0x4d >;
						linux,phandle = < 0xa1 >;
						phandle = < 0xa1 >;
					};
				};
			};

			dummy_sensor@41 {
				compatible = "trav-sensor3";
				reg = < 0x41 >;

				port {
					#address-cells = < 0x01 >;
					#size-cells = < 0x00 >;

					endpoint {
						reg = < 0x01 >;
						clock-lanes = < 0x00 >;
						data-lanes = < 0x01 0x02 0x03 0x04 >;
						remote-endpoint = < 0x4e >;
						linux,phandle = < 0xa2 >;
						phandle = < 0xa2 >;
					};
				};
			};

			dummy_sensor@42 {
				compatible = "trav-sensor3";
				reg = < 0x42 >;

				port {
					#address-cells = < 0x01 >;
					#size-cells = < 0x00 >;

					endpoint {
						reg = < 0x02 >;
						clock-lanes = < 0x00 >;
						data-lanes = < 0x01 0x02 0x03 0x04 >;
						remote-endpoint = < 0x4f >;
						linux,phandle = < 0xa3 >;
						phandle = < 0xa3 >;
					};
				};
			};

			dummy_sensor@43 {
				compatible = "trav-sensor3";
				reg = < 0x43 >;

				port {
					#address-cells = < 0x01 >;
					#size-cells = < 0x00 >;

					endpoint {
						reg = < 0x03 >;
						clock-lanes = < 0x00 >;
						data-lanes = < 0x01 0x02 0x03 0x04 >;
						remote-endpoint = < 0x50 >;
						linux,phandle = < 0xa4 >;
						phandle = < 0xa4 >;
					};
				};
			};

			dummy_sensor@44 {
				compatible = "trav-sensor3";
				reg = < 0x44 >;

				port {
					#address-cells = < 0x01 >;
					#size-cells = < 0x00 >;

					endpoint {
						reg = < 0x04 >;
						clock-lanes = < 0x00 >;
						data-lanes = < 0x01 0x02 0x03 0x04 >;
						remote-endpoint = < 0x51 >;
						linux,phandle = < 0xa5 >;
						phandle = < 0xa5 >;
					};
				};
			};

			dummy_sensor@45 {
				compatible = "trav-sensor3";
				reg = < 0x45 >;

				port {
					#address-cells = < 0x01 >;
					#size-cells = < 0x00 >;

					endpoint {
						reg = < 0x05 >;
						clock-lanes = < 0x00 >;
						data-lanes = < 0x01 0x02 0x03 0x04 >;
						remote-endpoint = < 0x52 >;
						linux,phandle = < 0xa6 >;
						phandle = < 0xa6 >;
					};
				};
			};

			dummy_sensor@46 {
				compatible = "trav-sensor3";
				reg = < 0x46 >;

				port {
					#address-cells = < 0x01 >;
					#size-cells = < 0x00 >;

					endpoint {
						reg = < 0x06 >;
						clock-lanes = < 0x00 >;
						data-lanes = < 0x01 0x02 0x03 0x04 >;
						remote-endpoint = < 0x53 >;
						linux,phandle = < 0xa7 >;
						phandle = < 0xa7 >;
					};
				};
			};

			dummy_sensor@47 {
				compatible = "trav-sensor3";
				reg = < 0x47 >;

				port {
					#address-cells = < 0x01 >;
					#size-cells = < 0x00 >;

					endpoint {
						reg = < 0x07 >;
						clock-lanes = < 0x00 >;
						data-lanes = < 0x01 0x02 0x03 0x04 >;
						remote-endpoint = < 0x54 >;
						linux,phandle = < 0xa8 >;
						phandle = < 0xa8 >;
					};
				};
			};
		};

		hsi2c@14220000 {
			compatible = "samsung,exynos7-hsi2c";
			reg = < 0x14220000 0x1000 >;
			interrupts = < 0x00 0x96 0x00 >;
			#address-cells = < 0x01 >;
			#size-cells = < 0x00 >;
			pinctrl-names = "default";
			pinctrl-0 = < 0x55 >;
			clocks = < 0x16 0x12 >;
			clock-names = "hsi2c";
			status = "okay";
		};

		hsi2c@14230000 {
			compatible = "samsung,exynos7-hsi2c";
			reg = < 0x14230000 0x1000 >;
			interrupts = < 0x00 0x97 0x00 >;
			#address-cells = < 0x01 >;
			#size-cells = < 0x00 >;
			pinctrl-names = "default";
			pinctrl-0 = < 0x56 >;
			clocks = < 0x16 0x13 >;
			clock-names = "hsi2c";
			status = "okay";
		};

		hsi2c@14240000 {
			compatible = "samsung,exynos7-hsi2c";
			reg = < 0x14240000 0x1000 >;
			interrupts = < 0x00 0x98 0x00 >;
			#address-cells = < 0x01 >;
			#size-cells = < 0x00 >;
			pinctrl-names = "default";
			pinctrl-0 = < 0x57 >;
			clocks = < 0x16 0x14 >;
			clock-names = "hsi2c";
			status = "okay";
		};

		hsi2c@14250000 {
			compatible = "samsung,exynos7-hsi2c";
			reg = < 0x14250000 0x1000 >;
			interrupts = < 0x00 0x99 0x00 >;
			#address-cells = < 0x01 >;
			#size-cells = < 0x00 >;
			pinctrl-names = "default";
			pinctrl-0 = < 0x58 >;
			clocks = < 0x16 0x15 >;
			clock-names = "hsi2c";
			status = "okay";

			tlv320aic3104@18 {
				#sound-dai-cells = < 0x00 >;
				compatible = "ti,tlv320aic3104";
				gpio-reset = < 0x59 0x06 0x01 >;
				reg = < 0x18 >;
				status = "okay";
				linux,phandle = < 0xf7 >;
				phandle = < 0xf7 >;
			};
		};

		hsi2c@14260000 {
			compatible = "samsung,exynos7-hsi2c";
			reg = < 0x14260000 0x1000 >;
			interrupts = < 0x00 0x9a 0x00 >;
			#address-cells = < 0x01 >;
			#size-cells = < 0x00 >;
			pinctrl-names = "default";
			pinctrl-0 = < 0x5a >;
			clocks = < 0x16 0x16 >;
			clock-names = "hsi2c";
			status = "okay";
		};

		hsi2c@14270000 {
			compatible = "samsung,exynos7-hsi2c";
			reg = < 0x14270000 0x1000 >;
			interrupts = < 0x00 0x9b 0x00 >;
			#address-cells = < 0x01 >;
			#size-cells = < 0x00 >;
			pinctrl-names = "default";
			pinctrl-0 = < 0x5b >;
			clocks = < 0x16 0x17 >;
			clock-names = "hsi2c";
			status = "okay";
		};

		phy@15100000 {
			compatible = "samsung,trav-usbdrd-phy";
			reg = < 0x15100000 0x100 >;
			#phy-cells = < 0x01 >;
			clocks = < 0x5c 0x0f 0x5c 0x12 >;
			clock-names = "phy\0ref";
			status = "okay";
			vbus-supply = < 0x5d >;
			linux,phandle = < 0x5e >;
			phandle = < 0x5e >;
		};

		usbdrd3 {
			compatible = "samsung,exynos7-dwusb3";
			#address-cells = < 0x01 >;
			#size-cells = < 0x01 >;
			ranges;
			clocks = < 0x5c 0x0d 0x5c 0x10 >;
			clock-names = "usbdrd30\0usbdrd30_axius_clk";

			dwc3@15200000 {
				compatible = "snps,dwc3";
				reg = < 0x15200000 0x10000 >;
				interrupts = < 0x00 0x51 0x04 >;
				phys = < 0x5e 0x00 >;
				phy-names = "usb2-phy";
				iommus = < 0x5f 0x03 0x01 >;
				status = "okay";
				dr_mode = "host";
			};
		};

		ufs0@15120000 {
			compatible = "turbo,trav-ufs";
			#address-cells = < 0x01 >;
			#size-cells = < 0x01 >;
			reg = < 0x15120000 0x200 0x15121100 0x200 0x15110000 0x8000 0x15130000 0x100 0x15124000 0x800 >;
			reg-names = "hci\0vs_hci\0unipro\0ufsp\0ufs_phy";
			interrupts = < 0x00 0x5b 0x00 >;
			pinctrl-names = "default";
			pinctrl-0 = < 0x60 0x61 0x62 >;
			clocks = < 0x5c 0x05 0x5c 0x07 >;
			clock-names = "core_clk\0sclk_unipro_main";
			freq-table-hz = < 0x00 0x00 0x00 0x00 >;
			pclk-freq-avail-range = < 0x16e3600 0x7ed6b40 >;
			ufs,pwr-local-l2-timer = < 0x1f40 0x6d60 0x4e20 >;
			ufs,pwr-remote-l2-timer = < 0x2ee0 0x7d00 0x3e80 >;
			ufs,ufs_addr_bus_width = < 0x24 >;
			ufs,pwr-attr-mode = "FAST";
			ufs,pwr-attr-lane = < 0x02 >;
			ufs,pwr-attr-gear = < 0x03 >;
			ufs,pwr-attr-hs-series = "HS_rate_b";
			ufs-rx-adv-fine-gran-sup_en = < 0x01 >;
			ufs-rx-adv-fine-gran-step = < 0x03 >;
			ufs-rx-adv-min-activate-time-cap = < 0x03 >;
			ufs-pa-granularity = < 0x06 >;
			ufs-pa-tacctivate = < 0x03 >;
			ufs-pa-hibern8time = < 0x02 >;
			iommus = < 0x5f 0x01 0x05 >;
			status = "okay";
		};

		ufs1@15160000 {
			compatible = "turbo,trav-ufs";
			#address-cells = < 0x01 >;
			#size-cells = < 0x01 >;
			reg = < 0x15160000 0x200 0x15161100 0x200 0x15150000 0x8000 0x15170000 0x100 0x15164000 0x800 >;
			reg-names = "hci\0vs_hci\0unipro\0ufsp\0ufs_phy";
			interrupts = < 0x00 0x5c 0x00 >;
			pinctrl-names = "default";
			pinctrl-0 = < 0x63 0x64 0x65 >;
			clocks = < 0x5c 0x09 0x5c 0x0b >;
			clock-names = "core_clk\0sclk_unipro_main";
			freq-table-hz = < 0x00 0x00 0x00 0x00 >;
			ufs,ufs_addr_bus_width = < 0x24 >;
			pclk-freq-avail-range = < 0x16e3600 0x7ed6b40 >;
			ufs,pwr-local-l2-timer = < 0x1f40 0x6d60 0x4e20 >;
			ufs,pwr-remote-l2-timer = < 0x2ee0 0x7d00 0x3e80 >;
			ufs,pwr-attr-mode = "FAST";
			ufs,pwr-attr-lane = < 0x02 >;
			ufs,pwr-attr-gear = < 0x03 >;
			ufs,pwr-attr-hs-series = "HS_rate_a";
			ufs-rx-adv-fine-gran-sup_en = < 0x01 >;
			ufs-rx-adv-fine-gran-step = < 0x03 >;
			ufs-rx-adv-min-activate-time-cap = < 0x03 >;
			ufs-pa-granularity = < 0x06 >;
			ufs-pa-tacctivate = < 0x03 >;
			ufs-pa-hibern8time = < 0x02 >;
			iommus = < 0x5f 0x02 0x01 >;
			status = "disabled";
		};

		mfc0@12880000 {
			compatible = "samsung,mfc-v12";
			reg = < 0x12880000 0x10000 >;
			interrupts = < 0x00 0x89 0x00 >;
			clock-names = "mfc";
			clocks = < 0x66 0x01 >;
			status = "okay";
			iommus = < 0x67 0x1000 0x00 0x67 0x1400 0x00 >;
		};

		mailbox@10080000 {
			compatible = "turbo,trav-mailbox-scs";
			reg = < 0x10080000 0x200 >;
			interrupts = < 0x00 0x1ac 0x00 0x00 0x1ad 0x00 >;
			#mbox-cells = < 0x01 >;
			memory-region = < 0x68 >;
		};

		mailbox@10090000 {
			compatible = "turbo,trav-mailbox-sms";
			reg = < 0x10090000 0x200 >;
			interrupts = < 0x00 0x1b0 0x00 0x00 0x1b1 0x00 >;
			#mbox-cells = < 0x01 >;

			mbox_sms_therm {
				compatible = "turbo,trav-mailbox-sms-therm";
				#thermal-sensor-cells = < 0x01 >;
				linux,phandle = < 0xde >;
				phandle = < 0xde >;
			};

			regulators {

				voltage_turbo_int {
					regulator-name = "VOLTAGE_TURBO_INT";
					regulator-min-microvolt = < 0x7a120 >;
					regulator-max-microvolt = < 0x155cc0 >;
					regulator-settling-time-up-us = < 0xc8 >;
					regulator-boot-on;
					regulator-always-on;
				};

				voltage_turbo_cpu {
					regulator-name = "VOLTAGE_TURBO_CPU";
					regulator-min-microvolt = < 0x99520 >;
					regulator-max-microvolt = < 0x12cc80 >;
					regulator-settling-time-up-us = < 0xc8 >;
					regulator-boot-on;
					regulator-always-on;
					linux,phandle = < 0x0f >;
					phandle = < 0x0f >;
				};

				voltage_turbo_gpu {
					regulator-name = "VOLTAGE_TURBO_GPU";
					regulator-min-microvolt = < 0x7a120 >;
					regulator-max-microvolt = < 0x155cc0 >;
					regulator-settling-time-up-us = < 0xc8 >;
					regulator-boot-on;
					regulator-always-on;
				};

				voltage_turbo_trip0 {
					regulator-name = "VOLTAGE_TURBO_TRIP0";
					regulator-min-microvolt = < 0x7a120 >;
					regulator-max-microvolt = < 0x155cc0 >;
					regulator-settling-time-up-us = < 0xc8 >;
					regulator-boot-on;
					regulator-always-on;
					linux,phandle = < 0xef >;
					phandle = < 0xef >;
				};

				voltage_turbo_trip1 {
					regulator-name = "VOLTAGE_TURBO_TRIP1";
					regulator-min-microvolt = < 0x7a120 >;
					regulator-max-microvolt = < 0x155cc0 >;
					regulator-settling-time-up-us = < 0xc8 >;
					regulator-boot-on;
					regulator-always-on;
				};
			};
		};

		smscan {
			compatible = "turbo,trav-smscan";
			memory-region = < 0x69 >;
		};

		ethernet@15300000 {
			compatible = "snps,dwc-qos-ethernet-4.21";
			reg = < 0x15300000 0x10000 >;
			interrupts = < 0x00 0x66 0x04 >;
			clocks = < 0x5c 0x17 0x5c 0x18 0x5c 0x19 0x5c 0x1a 0x5c 0x1b >;
			clock-names = "ptp\0aclk\0hclk\0rgmii\0rx";
			rx-clock-skew = < 0x6a 0x00 0x02 >;
			num-txq = < 0x01 >;
			num-rxq = < 0x01 >;
			iommus = < 0x5f 0x00 0x01 >;
			status = "okay";
			pinctrl-names = "default";
			pinctrl-0 = < 0x6b 0x6c 0x6d 0x6e 0x6f 0x70 0x71 0x72 >;
			local-mac-address = [ 45 54 48 30 4d 43 ];
			use-phy = "ETH0_PHY";
			rx-clock-skew-no-phy = < 0x6a 0x00 0x02 >;

			fixed-link {
				speed = < 0x3e8 >;
				full-duplex;
			};
		};

		ethernet@14300000 {
			compatible = "snps,dwc-qos-ethernet-4.21";
			reg = < 0x14300000 0x10000 >;
			interrupts = < 0x00 0xb0 0x04 >;
			clocks = < 0x16 0x21 0x16 0x22 0x16 0x23 0x16 0x24 0x16 0x25 0x16 0x26 0x16 0x27 >;
			clock-names = "ptp\0aclk\0hclk\0rgmii\0rx\0master_bus\0slave_bus";
			rx-clock-skew = < 0x73 0x10 0x02 >;
			rx-clock-mux = < 0x16 0x1000 0x01 >;
			num-txq = < 0x01 >;
			num-rxq = < 0x01 >;
			iommus = < 0x17 0x00 0x01 >;
			status = "okay";
			pinctrl-names = "default";
			pinctrl-0 = < 0x74 0x75 0x76 0x77 0x78 0x79 0x7a 0x7b >;
			local-mac-address = [ 45 54 48 31 4d 43 ];
			use-phy = "ETH1_PHY";
			rx-clock-skew-no-phy = < 0x73 0x10 0x00 >;

			fixed-link {
				speed = < 0x3e8 >;
				full-duplex;
			};
		};

		csis0@0x12640000 {
			compatible = "turbo,trav-csis";
			reg = < 0x12640000 0x1000 0x12641000 0x1000 0x12610000 0x3000 0x12630000 0x500 >;
			reg-names = "csis_ip_reg\0csis_dma_reg\0csis_pll_reg";
			interrupts = < 0x00 0x06 0x00 >;
			iommus = < 0x67 0x00 0x00 >;
			status = "okay";
			#address-cells = < 0x01 >;
			#size-cells = < 0x00 >;

			ports {
				#address-cells = < 0x01 >;
				#size-cells = < 0x00 >;

				port@0 {
					reg = < 0x00 >;

					endpoint {
						slave-mode;
						remote-endpoint = < 0x7c >;
						linux,phandle = < 0x30 >;
						phandle = < 0x30 >;
					};
				};
			};
		};

		csis1@0x12650000 {
			compatible = "turbo,trav-csis";
			reg = < 0x12650000 0x1000 0x12651000 0x1000 0x12610000 0x3000 0x12630000 0x500 >;
			reg-names = "csis_ip_reg\0csis_dma_reg\0csis_pll_reg";
			interrupts = < 0x00 0x07 0x00 >;
			iommus = < 0x67 0x00 0x00 >;
			status = "okay";
			#address-cells = < 0x01 >;
			#size-cells = < 0x00 >;

			ports {
				#address-cells = < 0x01 >;
				#size-cells = < 0x00 >;

				port@0 {
					reg = < 0x01 >;

					endpoint {
						slave-mode;
						remote-endpoint = < 0x7d >;
						linux,phandle = < 0x31 >;
						phandle = < 0x31 >;
					};
				};
			};
		};

		csis2@0x12660000 {
			compatible = "turbo,trav-csis";
			reg = < 0x12660000 0x1000 0x12661000 0x1000 0x12610000 0x3000 0x12630000 0x500 >;
			reg-names = "csis_ip_reg\0csis_dma_reg\0csis_pll_reg";
			interrupts = < 0x00 0x08 0x00 >;
			iommus = < 0x67 0x00 0x00 >;
			status = "okay";
			#address-cells = < 0x01 >;
			#size-cells = < 0x00 >;

			ports {
				#address-cells = < 0x01 >;
				#size-cells = < 0x00 >;

				port@0 {
					reg = < 0x02 >;

					endpoint {
						slave-mode;
						remote-endpoint = < 0x7e >;
						linux,phandle = < 0x32 >;
						phandle = < 0x32 >;
					};
				};
			};
		};

		csis3@0x12670000 {
			compatible = "turbo,trav-csis";
			reg = < 0x12670000 0x1000 0x12671000 0x1000 0x12610000 0x3000 0x12630000 0x500 >;
			reg-names = "csis_ip_reg\0csis_dma_reg\0csis_pll_reg";
			interrupts = < 0x00 0x09 0x00 >;
			iommus = < 0x67 0x00 0x00 >;
			status = "okay";
			#address-cells = < 0x01 >;
			#size-cells = < 0x00 >;

			ports {
				#address-cells = < 0x01 >;
				#size-cells = < 0x00 >;

				port@0 {
					reg = < 0x03 >;

					endpoint {
						slave-mode;
						remote-endpoint = < 0x7f >;
						linux,phandle = < 0x33 >;
						phandle = < 0x33 >;
					};
				};
			};
		};

		csis4@0x12680000 {
			compatible = "turbo,trav-csis";
			reg = < 0x12680000 0x1000 0x12681000 0x1000 0x12610000 0x3000 0x12630000 0x500 >;
			reg-names = "csis_ip_reg\0csis_dma_reg\0csis_pll_reg";
			interrupts = < 0x00 0x0a 0x00 >;
			iommus = < 0x67 0x00 0x00 >;
			status = "okay";
			#address-cells = < 0x01 >;
			#size-cells = < 0x00 >;

			ports {
				#address-cells = < 0x01 >;
				#size-cells = < 0x00 >;

				port@0 {
					reg = < 0x00 >;

					endpoint {
						slave-mode;
						remote-endpoint = < 0x80 >;
						linux,phandle = < 0x34 >;
						phandle = < 0x34 >;
					};
				};
			};
		};

		csis5@0x12690000 {
			compatible = "turbo,trav-csis";
			reg = < 0x12690000 0x1000 0x12691000 0x1000 0x12610000 0x3000 0x12630000 0x500 >;
			reg-names = "csis_ip_reg\0csis_dma_reg\0csis_pll_reg";
			interrupts = < 0x00 0x0b 0x00 >;
			iommus = < 0x67 0x00 0x00 >;
			status = "okay";
			#address-cells = < 0x01 >;
			#size-cells = < 0x00 >;

			ports {
				#address-cells = < 0x01 >;
				#size-cells = < 0x00 >;

				port@0 {
					reg = < 0x01 >;

					endpoint {
						slave-mode;
						remote-endpoint = < 0x81 >;
						linux,phandle = < 0x35 >;
						phandle = < 0x35 >;
					};
				};
			};
		};

		csis6@0x126A0000 {
			compatible = "turbo,trav-csis";
			reg = < 0x126a0000 0x1000 0x126a1000 0x1000 0x12610000 0x3000 0x12630000 0x500 >;
			reg-names = "csis_ip_reg\0csis_dma_reg\0csis_pll_reg";
			interrupts = < 0x00 0x0c 0x00 >;
			iommus = < 0x67 0x00 0x00 >;
			status = "okay";
			#address-cells = < 0x01 >;
			#size-cells = < 0x00 >;

			ports {
				#address-cells = < 0x01 >;
				#size-cells = < 0x00 >;

				port@0 {
					reg = < 0x02 >;

					endpoint {
						slave-mode;
						remote-endpoint = < 0x82 >;
						linux,phandle = < 0x36 >;
						phandle = < 0x36 >;
					};
				};
			};
		};

		csis7@0x126B0000 {
			compatible = "turbo,trav-csis";
			reg = < 0x126b0000 0x1000 0x126b1000 0x1000 0x12610000 0x3000 0x12630000 0x500 >;
			reg-names = "csis_ip_reg\0csis_dma_reg\0csis_pll_reg";
			interrupts = < 0x00 0x0d 0x00 >;
			iommus = < 0x67 0x00 0x00 >;
			status = "okay";
			#address-cells = < 0x01 >;
			#size-cells = < 0x00 >;

			ports {
				#address-cells = < 0x01 >;
				#size-cells = < 0x00 >;

				port@0 {
					reg = < 0x03 >;

					endpoint {
						slave-mode;
						remote-endpoint = < 0x83 >;
						linux,phandle = < 0x37 >;
						phandle = < 0x37 >;
					};
				};
			};
		};

		csis8@0x126C0000 {
			compatible = "turbo,trav-csis";
			reg = < 0x126c0000 0x1000 0x126c1000 0x1000 0x12610000 0x3000 0x12630000 0x500 >;
			reg-names = "csis_ip_reg\0csis_dma_reg\0csis_pll_reg";
			interrupts = < 0x00 0x0e 0x00 >;
			iommus = < 0x67 0x00 0x00 >;
			status = "okay";
			#address-cells = < 0x01 >;
			#size-cells = < 0x00 >;

			ports {
				#address-cells = < 0x01 >;
				#size-cells = < 0x00 >;

				port@0 {
					reg = < 0x00 >;

					endpoint {
						slave-mode;
						remote-endpoint = < 0x84 >;
						linux,phandle = < 0x38 >;
						phandle = < 0x38 >;
					};
				};
			};
		};

		csis9@0x126D0000 {
			compatible = "turbo,trav-csis";
			reg = < 0x126d0000 0x1000 0x126d1000 0x1000 0x12610000 0x3000 0x12630000 0x500 >;
			reg-names = "csis_ip_reg\0csis_dma_reg\0csis_pll_reg";
			interrupts = < 0x00 0x0f 0x00 >;
			iommus = < 0x67 0x00 0x00 >;
			status = "okay";
			#address-cells = < 0x01 >;
			#size-cells = < 0x00 >;

			ports {
				#address-cells = < 0x01 >;
				#size-cells = < 0x00 >;

				port@0 {
					reg = < 0x01 >;

					endpoint {
						slave-mode;
						remote-endpoint = < 0x85 >;
						linux,phandle = < 0x39 >;
						phandle = < 0x39 >;
					};
				};
			};
		};

		csis10@0x126E0000 {
			compatible = "turbo,trav-csis";
			reg = < 0x126e0000 0x1000 0x126e1000 0x1000 0x12610000 0x3000 0x12630000 0x500 >;
			reg-names = "csis_ip_reg\0csis_dma_reg\0csis_pll_reg";
			interrupts = < 0x00 0x10 0x00 >;
			iommus = < 0x67 0x00 0x00 >;
			status = "okay";
			#address-cells = < 0x01 >;
			#size-cells = < 0x00 >;

			ports {
				#address-cells = < 0x01 >;
				#size-cells = < 0x00 >;

				port@0 {
					reg = < 0x02 >;

					endpoint {
						slave-mode;
						remote-endpoint = < 0x86 >;
						linux,phandle = < 0x3a >;
						phandle = < 0x3a >;
					};
				};
			};
		};

		csis11@0x126F0000 {
			compatible = "turbo,trav-csis";
			reg = < 0x126f0000 0x1000 0x126f1000 0x1000 0x12610000 0x3000 0x12630000 0x500 >;
			reg-names = "csis_ip_reg\0csis_dma_reg\0csis_pll_reg";
			interrupts = < 0x00 0x11 0x00 >;
			iommus = < 0x67 0x00 0x00 >;
			status = "okay";
			#address-cells = < 0x01 >;
			#size-cells = < 0x00 >;

			ports {
				#address-cells = < 0x01 >;
				#size-cells = < 0x00 >;

				port@0 {
					reg = < 0x03 >;

					endpoint {
						slave-mode;
						remote-endpoint = < 0x87 >;
						linux,phandle = < 0x3b >;
						phandle = < 0x3b >;
					};
				};
			};
		};

		dprx0@14ec0000 {
			compatible = "trav-dprx";
			reg = < 0x14ec0000 0x10000 0x14e50000 0x10000 >;
			reg-names = "dprx_ip_reg\0dprx_dma_reg";
			interrupts = < 0x00 0x133 0x00 0x00 0x132 0x00 >;
			clock-names = "dp_clk0\0dp_clk1\0dp_clk2\0dp_clk3\0dp_clk4\0dp_clk5\0dp_clk6\0dp_clk7\0dp_clk8\0dp_clk9\0dp_clk10\0dp_clk11\0dp_clk12\0dp_clk13\0dp_clk14";
			clocks = < 0x88 0x01 0x88 0x03 0x88 0x05 0x88 0x07 0x88 0x09 0x88 0x0b 0x88 0x0c 0x88 0x0d 0x88 0x0e 0x88 0x0f 0x88 0x10 0x88 0x11 0x88 0x13 0x88 0x14 0x88 0x15 >;
			iommus = < 0x67 0x1800 0x00 >;
			status = "disabled";
			#address-cells = < 0x01 >;
			#size-cells = < 0x00 >;

			ports {
				#address-cells = < 0x01 >;
				#size-cells = < 0x00 >;

				port@0 {
					reg = < 0x00 >;

					endpoint {
						slave-mode;
						remote-endpoint = < 0x89 >;
						linux,phandle = < 0x3d >;
						phandle = < 0x3d >;
					};
				};

				port@1 {
					reg = < 0x01 >;

					endpoint {
						slave-mode;
						remote-endpoint = < 0x8a >;
						linux,phandle = < 0x3e >;
						phandle = < 0x3e >;
					};
				};

				port@2 {
					reg = < 0x02 >;

					endpoint {
						slave-mode;
						remote-endpoint = < 0x8b >;
						linux,phandle = < 0x3f >;
						phandle = < 0x3f >;
					};
				};

				port@3 {
					reg = < 0x03 >;

					endpoint {
						slave-mode;
						remote-endpoint = < 0x8c >;
						linux,phandle = < 0x40 >;
						phandle = < 0x40 >;
					};
				};

				port@4 {
					reg = < 0x04 >;

					endpoint {
						slave-mode;
						remote-endpoint = < 0x8d >;
						linux,phandle = < 0x41 >;
						phandle = < 0x41 >;
					};
				};

				port@5 {
					reg = < 0x05 >;

					endpoint {
						slave-mode;
						remote-endpoint = < 0x8e >;
						linux,phandle = < 0x42 >;
						phandle = < 0x42 >;
					};
				};

				port@6 {
					reg = < 0x06 >;

					endpoint {
						slave-mode;
						remote-endpoint = < 0x8f >;
						linux,phandle = < 0x43 >;
						phandle = < 0x43 >;
					};
				};

				port@7 {
					reg = < 0x07 >;

					endpoint {
						slave-mode;
						remote-endpoint = < 0x90 >;
						linux,phandle = < 0x44 >;
						phandle = < 0x44 >;
					};
				};
			};
		};

		dprx1@14e80000 {
			compatible = "trav-dprx";
			reg = < 0x14e80000 0x10000 0x14e40000 0x10000 >;
			reg-names = "dprx_ip_reg\0dprx_dma_reg";
			interrupts = < 0x00 0x135 0x00 0x00 0x134 0x00 >;
			clock-names = "dp_clk0\0dp_clk1\0dp_clk2\0dp_clk3\0dp_clk4\0dp_clk5\0dp_clk6\0dp_clk7\0dp_clk8\0dp_clk9\0dp_clk10\0dp_clk11\0dp_clk12\0dp_clk13\0dp_clk14";
			clocks = < 0x88 0x02 0x88 0x04 0x88 0x06 0x88 0x08 0x88 0x0a 0x88 0x0b 0x88 0x0c 0x88 0x0d 0x88 0x0e 0x88 0x0f 0x88 0x10 0x88 0x12 0x88 0x13 0x88 0x14 0x88 0x15 >;
			iommus = < 0x67 0x1800 0x00 >;
			status = "disabled";
			#address-cells = < 0x01 >;
			#size-cells = < 0x00 >;

			ports {
				#address-cells = < 0x01 >;
				#size-cells = < 0x00 >;

				port@0 {
					reg = < 0x00 >;

					endpoint {
						slave-mode;
						remote-endpoint = < 0x91 >;
						linux,phandle = < 0x45 >;
						phandle = < 0x45 >;
					};
				};

				port@1 {
					reg = < 0x01 >;

					endpoint {
						slave-mode;
						remote-endpoint = < 0x92 >;
						linux,phandle = < 0x46 >;
						phandle = < 0x46 >;
					};
				};

				port@2 {
					reg = < 0x02 >;

					endpoint {
						slave-mode;
						remote-endpoint = < 0x93 >;
						linux,phandle = < 0x47 >;
						phandle = < 0x47 >;
					};
				};

				port@3 {
					reg = < 0x03 >;

					endpoint {
						slave-mode;
						remote-endpoint = < 0x94 >;
						linux,phandle = < 0x48 >;
						phandle = < 0x48 >;
					};
				};

				port@4 {
					reg = < 0x04 >;

					endpoint {
						slave-mode;
						remote-endpoint = < 0x95 >;
						linux,phandle = < 0x49 >;
						phandle = < 0x49 >;
					};
				};

				port@5 {
					reg = < 0x05 >;

					endpoint {
						slave-mode;
						remote-endpoint = < 0x96 >;
						linux,phandle = < 0x4a >;
						phandle = < 0x4a >;
					};
				};

				port@6 {
					reg = < 0x06 >;

					endpoint {
						slave-mode;
						remote-endpoint = < 0x97 >;
						linux,phandle = < 0x4b >;
						phandle = < 0x4b >;
					};
				};

				port@7 {
					reg = < 0x07 >;

					endpoint {
						slave-mode;
						remote-endpoint = < 0x98 >;
						linux,phandle = < 0x4c >;
						phandle = < 0x4c >;
					};
				};
			};
		};

		dprx2@14cc0000 {
			compatible = "trav-dprx";
			reg = < 0x14cc0000 0x10000 0x14c50000 0x10000 >;
			reg-names = "dprx_ip_reg\0dprx_dma_reg";
			interrupts = < 0x00 0x137 0x00 0x00 0x136 0x00 >;
			clock-names = "dp_clk0\0dp_clk1\0dp_clk2\0dp_clk3\0dp_clk4\0dp_clk5\0dp_clk6\0dp_clk7\0dp_clk8\0dp_clk9\0dp_clk10\0dp_clk11\0dp_clk12\0dp_clk13\0dp_clk14\0dp_clk15";
			clocks = < 0x1d 0x03 0x1d 0x05 0x1d 0x07 0x1d 0x09 0x1d 0x0b 0x1d 0x0d 0x1d 0x0e 0x1d 0x0f 0x1d 0x10 0x1d 0x11 0x1d 0x12 0x1d 0x13 0x1d 0x15 0x1d 0x16 0x1d 0x17 0x1d 0x18 >;
			iommus = < 0x67 0x400 0x00 >;
			status = "disabled";
			#address-cells = < 0x01 >;
			#size-cells = < 0x00 >;

			ports {
				#address-cells = < 0x01 >;
				#size-cells = < 0x00 >;

				port@0 {
					reg = < 0x00 >;

					endpoint {
						slave-mode;
						remote-endpoint = < 0x99 >;
						linux,phandle = < 0x4d >;
						phandle = < 0x4d >;
					};
				};

				port@1 {
					reg = < 0x01 >;

					endpoint {
						slave-mode;
						remote-endpoint = < 0x9a >;
						linux,phandle = < 0x4e >;
						phandle = < 0x4e >;
					};
				};

				port@2 {
					reg = < 0x02 >;

					endpoint {
						slave-mode;
						remote-endpoint = < 0x9b >;
						linux,phandle = < 0x4f >;
						phandle = < 0x4f >;
					};
				};

				port@3 {
					reg = < 0x03 >;

					endpoint {
						slave-mode;
						remote-endpoint = < 0x9c >;
						linux,phandle = < 0x50 >;
						phandle = < 0x50 >;
					};
				};

				port@4 {
					reg = < 0x04 >;

					endpoint {
						slave-mode;
						remote-endpoint = < 0x9d >;
						linux,phandle = < 0x51 >;
						phandle = < 0x51 >;
					};
				};

				port@5 {
					reg = < 0x05 >;

					endpoint {
						slave-mode;
						remote-endpoint = < 0x9e >;
						linux,phandle = < 0x52 >;
						phandle = < 0x52 >;
					};
				};

				port@6 {
					reg = < 0x06 >;

					endpoint {
						slave-mode;
						remote-endpoint = < 0x9f >;
						linux,phandle = < 0x53 >;
						phandle = < 0x53 >;
					};
				};

				port@7 {
					reg = < 0x07 >;

					endpoint {
						slave-mode;
						remote-endpoint = < 0xa0 >;
						linux,phandle = < 0x54 >;
						phandle = < 0x54 >;
					};
				};
			};
		};

		dprx3@14c80000 {
			compatible = "trav-dprx";
			reg = < 0x14c80000 0x10000 0x14c40000 0x10000 >;
			reg-names = "dprx_ip_reg\0dprx_dma_reg";
			interrupts = < 0x00 0x139 0x00 0x00 0x138 0x00 >;
			clock-names = "dp_clk0\0dp_clk1\0dp_clk2\0dp_clk3\0dp_clk4\0dp_clk5\0dp_clk6\0dp_clk7\0dp_clk8\0dp_clk9\0dp_clk10\0dp_clk11\0dp_clk12\0dp_clk13\0dp_clk14\0dp_clk15";
			clocks = < 0x1d 0x04 0x1d 0x06 0x1d 0x08 0x1d 0x0a 0x1d 0x0c 0x1d 0x0d 0x1d 0x0e 0x1d 0x0f 0x1d 0x10 0x1d 0x11 0x1d 0x12 0x1d 0x14 0x1d 0x15 0x1d 0x16 0x1d 0x17 0x1d 0x18 >;
			iommus = < 0x67 0x400 0x00 >;
			status = "disabled";
			#address-cells = < 0x01 >;
			#size-cells = < 0x00 >;

			ports {
				#address-cells = < 0x01 >;
				#size-cells = < 0x00 >;

				port@0 {
					reg = < 0x00 >;

					endpoint {
						slave-mode;
						remote-endpoint = < 0xa1 >;
					};
				};

				port@1 {
					reg = < 0x01 >;

					endpoint {
						slave-mode;
						remote-endpoint = < 0xa2 >;
					};
				};

				port@2 {
					reg = < 0x02 >;

					endpoint {
						slave-mode;
						remote-endpoint = < 0xa3 >;
					};
				};

				port@3 {
					reg = < 0x03 >;

					endpoint {
						slave-mode;
						remote-endpoint = < 0xa4 >;
					};
				};

				port@4 {
					reg = < 0x04 >;

					endpoint {
						slave-mode;
						remote-endpoint = < 0xa5 >;
					};
				};

				port@5 {
					reg = < 0x05 >;

					endpoint {
						slave-mode;
						remote-endpoint = < 0xa6 >;
					};
				};

				port@6 {
					reg = < 0x06 >;

					endpoint {
						slave-mode;
						remote-endpoint = < 0xa7 >;
					};
				};

				port@7 {
					reg = < 0x07 >;

					endpoint {
						slave-mode;
						remote-endpoint = < 0xa8 >;
					};
				};
			};
		};

		pcie-phy@15080000 {
			compatible = "samsung,trav-pcie-phy";
			#phy-cells = < 0x00 >;
			reg = < 0x15080000 0x2000 0x150a0000 0x1000 >;
			reg-names = "phy\0pcs";
			samsung,pmureg-phandle = < 0x20 >;
			samsung,fsys-sysreg = < 0x6a >;
			phy-mode = < 0x00 >;
			status = "PCIE4PHY";
			linux,phandle = < 0xaa >;
			phandle = < 0xaa >;
		};

		pcie-phy@16880000 {
			compatible = "samsung,trav-pcie-phy";
			#phy-cells = < 0x00 >;
			reg = < 0x16880000 0x2000 0x16860000 0x1000 >;
			reg-names = "phy\0pcs";
			samsung,pmureg-phandle = < 0x20 >;
			samsung,fsys-sysreg = < 0xa9 >;
			phy-mode = < 0x00 >;
			status = "PCIE0PHY";
			linux,phandle = < 0xaf >;
			phandle = < 0xaf >;
		};

		pcie4_rc@15400000 {
			compatible = "samsung,trav-pcie\0snps,dw-pcie";
			clocks = < 0x5c 0x14 0x5c 0x13 0x5c 0x15 0x5c 0x16 >;
			clock-names = "aux_clk\0dbi_clk\0mstr_clk\0slv_clk";
			#address-cells = < 0x03 >;
			#size-cells = < 0x02 >;
			device_type = "pci";
			interrupts = < 0x00 0x5d 0x04 >;
			interrupt-names = "intr";
			num-lanes = < 0x04 >;
			reg = < 0x15090000 0x1000 0x15400000 0x1000 0x15800000 0x1000 >;
			reg-names = "elbi\0dbi\0config";
			ranges = < 0x82000000 0x00 0x15801000 0x15801000 0x00 0xfeefff >;
			samsung,fsys-sysreg = < 0x6a >;
			phys = < 0xaa >;
			iommu-map = < 0x00 0x5f 0x04 0x10000 >;
			iommu-map-mask = < 0x00 >;
			phy-names = "pcie_phy0";
			status = "PCIE4STS";
			pinctrl-names = "default";
			pinctrl-0 = < 0xab 0xac 0xad >;
		};

		pcie4_ep@15400000 {
			compatible = "samsung,trav-pcie-ep\0snps,dw-pcie";
			clocks = < 0x5c 0x14 0x5c 0x13 0x5c 0x15 0x5c 0x16 >;
			clock-names = "aux_clk\0dbi_clk\0mstr_clk\0slv_clk";
			interrupts = < 0x00 0x5d 0x04 >;
			interrupt-names = "intr";
			reg = < 0x15090000 0x1000 0x15400000 0x1000 0x15401000 0x80 0x15800000 0xff0000 >;
			reg-names = "elbi\0ep_dbics\0ep_dbics2\0addr_space";
			num-lanes = < 0x04 >;
			num-ib-windows = < 0x10 >;
			num-ob-windows = < 0x10 >;
			samsung,fsys-sysreg = < 0x6a >;
			phys = < 0xaa >;
			iommu-map = < 0x00 0x5f 0x04 0x10000 >;
			iommu-map-mask = < 0x00 >;
			phy-names = "pcie_phy0";
			status = "disabled";
			pinctrl-names = "default";
			pinctrl-0 = < 0xab 0xac 0xad >;
		};

		pcie0_rc@16A00000 {
			compatible = "samsung,trav-pcie\0snps,dw-pcie";
			clocks = < 0xae 0x02 0xae 0x01 0xae 0x03 0xae 0x04 >;
			clock-names = "aux_clk\0dbi_clk\0mstr_clk\0slv_clk";
			#address-cells = < 0x03 >;
			#size-cells = < 0x02 >;
			device_type = "pci";
			interrupts = < 0x00 0x73 0x04 >;
			interrupt-names = "intr";
			num-lanes = < 0x04 >;
			reg = < 0x168b0000 0x1000 0x16a00000 0x1000 0x17000000 0x1000 >;
			reg-names = "elbi\0dbi\0config";
			ranges = < 0x82000000 0x00 0x17001000 0x17001000 0x00 0xfeefff >;
			samsung,fsys-sysreg = < 0xa9 >;
			phys = < 0xaf >;
			phy-names = "pcie_phy1";
			iommu-map = < 0x00 0x15 0x00 0x10000 >;
			iommu-map-mask = < 0x00 >;
			status = "PCIE0STS";
			pinctrl-names = "default";
			pinctrl-0 = < 0xb0 0xb1 0xb2 >;
		};

		pcie0_ep@16A00000 {
			compatible = "samsung,trav-pcie-ep\0snps,dw-pcie";
			clocks = < 0xae 0x02 0xae 0x01 0xae 0x03 0xae 0x04 >;
			clock-names = "aux_clk\0dbi_clk\0mstr_clk\0slv_clk";
			interrupts = < 0x00 0x73 0x04 >;
			interrupt-names = "intr";
			reg = < 0x168b0000 0x1000 0x16a00000 0x1000 0x16a01000 0x80 0x17000000 0xff0000 >;
			reg-names = "elbi\0ep_dbics\0ep_dbics2\0addr_space";
			num-lanes = < 0x04 >;
			num-ib-windows = < 0x10 >;
			num-ob-windows = < 0x10 >;
			samsung,fsys-sysreg = < 0xa9 >;
			phys = < 0xaf >;
			phy-names = "pcie_phy1";
			iommu-map = < 0x00 0x15 0x00 0x10000 >;
			iommu-map-mask = < 0x00 >;
			status = "PCIE0EPSTS";
			pinctrl-names = "default";
			pinctrl-0 = < 0xb0 0xb1 0xb2 >;
		};

		pcie1_rc@16B00000 {
			compatible = "samsung,trav-pcie\0snps,dw-pcie";
			clocks = < 0xae 0x06 0xae 0x05 0xae 0x07 0xae 0x08 >;
			clock-names = "aux_clk\0dbi_clk\0mstr_clk\0slv_clk";
			#address-cells = < 0x03 >;
			#size-cells = < 0x02 >;
			device_type = "pci";
			interrupts = < 0x00 0x75 0x04 >;
			interrupt-names = "intr";
			num-lanes = < 0x04 >;
			reg = < 0x168c0000 0x1000 0x16b00000 0x1000 0x18000000 0x1000 >;
			reg-names = "elbi\0dbi\0config";
			ranges = < 0x82000000 0x00 0x18001000 0x18001000 0x00 0xfeefff >;
			samsung,fsys-sysreg = < 0xa9 >;
			phys = < 0xaf >;
			phy-names = "pcie_phy1";
			status = "disabled";
			pinctrl-names = "default";
			pinctrl-0 = < 0xb0 0xb3 0xb2 >;
		};

		pcie1_ep@16B00000 {
			compatible = "samsung,trav-pcie-ep\0snps,dw-pcie";
			clocks = < 0xae 0x06 0xae 0x05 0xae 0x07 0xae 0x08 >;
			clock-names = "aux_clk\0dbi_clk\0mstr_clk\0slv_clk";
			interrupts = < 0x00 0x75 0x04 >;
			interrupt-names = "intr";
			reg = < 0x168c0000 0x1000 0x16b00000 0x1000 0x16b01000 0x80 0x18000000 0xff0000 >;
			reg-names = "elbi\0ep_dbics\0ep_dbics2\0addr_space";
			num-lanes = < 0x04 >;
			num-ib-windows = < 0x10 >;
			num-ob-windows = < 0x10 >;
			samsung,fsys-sysreg = < 0xa9 >;
			phys = < 0xaf >;
			phy-names = "pcie_phy1";
			status = "disabled";
			pinctrl-names = "default";
			pinctrl-0 = < 0xb0 0xb3 0xb2 >;
		};

		can@0x14080000 {
			compatible = "bosch,m_can";
			reg = < 0x14088000 0x200 0x14080000 0x8000 >;
			reg-names = "m_can\0message_ram";
			interrupts = < 0x00 0x9f 0x04 0x00 0xa0 0x04 >;
			interrupt-names = "int0\0int1";
			clocks = < 0x16 0x19 0x16 0x18 >;
			clock-names = "hclk\0cclk";
			syscon-mraminit = < 0x73 0x700 >;
			bosch,mram-cfg = < 0x00 0x80 0x40 0x40 0x40 0x40 0x20 0x20 >;
			status = "okay";
			pinctrl-names = "default";
			pinctrl-0 = < 0xb4 >;
		};

		can@0x14090000 {
			compatible = "bosch,m_can";
			reg = < 0x14098000 0x200 0x14090000 0x8000 >;
			reg-names = "m_can\0message_ram";
			interrupts = < 0x00 0xa2 0x04 0x00 0xa3 0x04 >;
			interrupt-names = "int0\0int1";
			clocks = < 0x16 0x1b 0x16 0x1a >;
			clock-names = "hclk\0cclk";
			syscon-mraminit = < 0x73 0x704 >;
			bosch,mram-cfg = < 0x00 0x80 0x40 0x40 0x40 0x40 0x20 0x20 >;
			status = "okay";
			pinctrl-names = "default";
			pinctrl-0 = < 0xb5 >;
		};

		can@0x140a0000 {
			compatible = "bosch,m_can";
			reg = < 0x140a8000 0x200 0x140a0000 0x8000 >;
			reg-names = "m_can\0message_ram";
			interrupts = < 0x00 0xa5 0x04 0x00 0xa6 0x04 >;
			interrupt-names = "int0\0int1";
			clocks = < 0x16 0x1d 0x16 0x1c >;
			clock-names = "hclk\0cclk";
			syscon-mraminit = < 0x73 0x708 >;
			bosch,mram-cfg = < 0x00 0x80 0x40 0x40 0x40 0x40 0x20 0x20 >;
			status = "okay";
			pinctrl-names = "default";
			pinctrl-0 = < 0xb6 >;
		};

		can@0x140b0000 {
			compatible = "bosch,m_can";
			reg = < 0x140b8000 0x200 0x140b0000 0x8000 >;
			reg-names = "m_can\0message_ram";
			interrupts = < 0x00 0xa8 0x04 0x00 0xa9 0x04 >;
			interrupt-names = "int0\0int1";
			clocks = < 0x16 0x1f 0x16 0x1e >;
			clock-names = "hclk\0cclk";
			syscon-mraminit = < 0x73 0x70c >;
			bosch,mram-cfg = < 0x00 0x80 0x40 0x40 0x40 0x40 0x20 0x20 >;
			status = "okay";
			pinctrl-names = "default";
			pinctrl-0 = < 0xb7 >;
		};

		adc@141a0000 {
			compatible = "samsung,trav-adc";
			reg = < 0x141a0000 0x100 >;
			interrupts = < 0x00 0xad 0x00 >;
			clocks = < 0x16 0x20 >;
			clock-names = "adc";
			#io-channel-cells = < 0x01 >;
			io-channel-ranges;
			status = "okay";
		};

		funnel@13009000 {
			compatible = "arm,coresight-funnel\0arm,primecell";
			reg = < 0x13009000 0x1000 >;
			clocks = < 0x18 >;
			clock-names = "apb_pclk";

			ports {
				#address-cells = < 0x01 >;
				#size-cells = < 0x00 >;

				port@4 {
					reg = < 0x04 >;

					endpoint {
						slave-mode;
						remote-endpoint = < 0xb8 >;
						linux,phandle = < 0xd2 >;
						phandle = < 0xd2 >;
					};
				};

				port@5 {
					reg = < 0x05 >;

					endpoint {
						slave-mode;
						remote-endpoint = < 0xb9 >;
						linux,phandle = < 0xd3 >;
						phandle = < 0xd3 >;
					};
				};

				port@6 {
					reg = < 0x06 >;

					endpoint {
						slave-mode;
						remote-endpoint = < 0xba >;
						linux,phandle = < 0xd4 >;
						phandle = < 0xd4 >;
					};
				};

				port@7 {
					reg = < 0x07 >;

					endpoint {
						slave-mode;
						remote-endpoint = < 0xbb >;
						linux,phandle = < 0xd5 >;
						phandle = < 0xd5 >;
					};
				};

				port@8 {
					reg = < 0x00 >;

					endpoint {
						remote-endpoint = < 0xbc >;
						linux,phandle = < 0xcc >;
						phandle = < 0xcc >;
					};
				};
			};
		};

		funnel@13008000 {
			compatible = "arm,coresight-funnel\0arm,primecell";
			reg = < 0x13008000 0x1000 >;
			clocks = < 0x18 >;
			clock-names = "apb_pclk";

			ports {
				#address-cells = < 0x01 >;
				#size-cells = < 0x00 >;

				port@4 {
					reg = < 0x04 >;

					endpoint {
						slave-mode;
						remote-endpoint = < 0xbd >;
						linux,phandle = < 0xd6 >;
						phandle = < 0xd6 >;
					};
				};

				port@5 {
					reg = < 0x05 >;

					endpoint {
						slave-mode;
						remote-endpoint = < 0xbe >;
						linux,phandle = < 0xd7 >;
						phandle = < 0xd7 >;
					};
				};

				port@6 {
					reg = < 0x06 >;

					endpoint {
						slave-mode;
						remote-endpoint = < 0xbf >;
						linux,phandle = < 0xd8 >;
						phandle = < 0xd8 >;
					};
				};

				port@7 {
					reg = < 0x07 >;

					endpoint {
						slave-mode;
						remote-endpoint = < 0xc0 >;
						linux,phandle = < 0xd9 >;
						phandle = < 0xd9 >;
					};
				};

				port@8 {
					reg = < 0x00 >;

					endpoint {
						remote-endpoint = < 0xc1 >;
						linux,phandle = < 0xce >;
						phandle = < 0xce >;
					};
				};
			};
		};

		funnel@13007000 {
			compatible = "arm,coresight-funnel\0arm,primecell";
			reg = < 0x13007000 0x1000 >;
			clocks = < 0x18 >;
			clock-names = "apb_pclk";

			ports {
				#address-cells = < 0x01 >;
				#size-cells = < 0x00 >;

				port@4 {
					reg = < 0x04 >;

					endpoint {
						slave-mode;
						remote-endpoint = < 0xc2 >;
						linux,phandle = < 0xda >;
						phandle = < 0xda >;
					};
				};

				port@5 {
					reg = < 0x05 >;

					endpoint {
						slave-mode;
						remote-endpoint = < 0xc3 >;
						linux,phandle = < 0xdb >;
						phandle = < 0xdb >;
					};
				};

				port@6 {
					reg = < 0x06 >;

					endpoint {
						slave-mode;
						remote-endpoint = < 0xc4 >;
						linux,phandle = < 0xdc >;
						phandle = < 0xdc >;
					};
				};

				port@7 {
					reg = < 0x07 >;

					endpoint {
						slave-mode;
						remote-endpoint = < 0xc5 >;
						linux,phandle = < 0xdd >;
						phandle = < 0xdd >;
					};
				};

				port@8 {
					reg = < 0x00 >;

					endpoint {
						remote-endpoint = < 0xc6 >;
						linux,phandle = < 0xd0 >;
						phandle = < 0xd0 >;
					};
				};
			};
		};

		funnel@1300A000 {
			compatible = "arm,coresight-funnel\0arm,primecell";
			reg = < 0x1300a000 0x1000 >;
			clocks = < 0x18 >;
			clock-names = "apb_pclk";

			ports {
				#address-cells = < 0x01 >;
				#size-cells = < 0x00 >;

				port@0 {
					reg = < 0x00 >;

					endpoint {
						slave-mode;
						remote-endpoint = < 0xc7 >;
						linux,phandle = < 0xcf >;
						phandle = < 0xcf >;
					};
				};

				port@1 {
					reg = < 0x01 >;

					endpoint {
						slave-mode;
						remote-endpoint = < 0xc8 >;
						linux,phandle = < 0xcd >;
						phandle = < 0xcd >;
					};
				};

				port@2 {
					reg = < 0x02 >;

					endpoint {
						slave-mode;
						remote-endpoint = < 0xc9 >;
						linux,phandle = < 0xcb >;
						phandle = < 0xcb >;
					};
				};

				port@4 {
					reg = < 0x00 >;

					endpoint {
						remote-endpoint = < 0xca >;
						linux,phandle = < 0xd1 >;
						phandle = < 0xd1 >;
					};
				};
			};
		};

		etf@13005000 {
			compatible = "arm,coresight-tmc\0arm,primecell";
			reg = < 0x13005000 0x1000 >;
			clocks = < 0x18 >;
			clock-names = "apb_pclk";

			ports {
				#address-cells = < 0x01 >;
				#size-cells = < 0x00 >;

				port@0 {
					reg = < 0x00 >;

					endpoint {
						slave-mode;
						remote-endpoint = < 0xcb >;
						linux,phandle = < 0xc9 >;
						phandle = < 0xc9 >;
					};
				};

				port@1 {
					reg = < 0x00 >;

					endpoint {
						slave-mode;
						remote-endpoint = < 0xcc >;
						linux,phandle = < 0xbc >;
						phandle = < 0xbc >;
					};
				};
			};
		};

		etf@13004000 {
			compatible = "arm,coresight-tmc\0arm,primecell";
			reg = < 0x13004000 0x1000 >;
			clocks = < 0x18 >;
			clock-names = "apb_pclk";

			ports {
				#address-cells = < 0x01 >;
				#size-cells = < 0x00 >;

				port@0 {
					reg = < 0x00 >;

					endpoint {
						slave-mode;
						remote-endpoint = < 0xcd >;
						linux,phandle = < 0xc8 >;
						phandle = < 0xc8 >;
					};
				};

				port@1 {
					reg = < 0x00 >;

					endpoint {
						slave-mode;
						remote-endpoint = < 0xce >;
						linux,phandle = < 0xc1 >;
						phandle = < 0xc1 >;
					};
				};
			};
		};

		etf@13003000 {
			compatible = "arm,coresight-tmc\0arm,primecell";
			reg = < 0x13003000 0x1000 >;
			clocks = < 0x18 >;
			clock-names = "apb_pclk";

			ports {
				#address-cells = < 0x01 >;
				#size-cells = < 0x00 >;

				port@0 {
					reg = < 0x00 >;

					endpoint {
						slave-mode;
						remote-endpoint = < 0xcf >;
						linux,phandle = < 0xc7 >;
						phandle = < 0xc7 >;
					};
				};

				port@1 {
					reg = < 0x00 >;

					endpoint {
						slave-mode;
						remote-endpoint = < 0xd0 >;
						linux,phandle = < 0xc6 >;
						phandle = < 0xc6 >;
					};
				};
			};
		};

		etr@1300B000 {
			compatible = "arm,coresight-tmc\0arm,primecell";
			reg = < 0x1300b000 0x1000 >;
			clocks = < 0x18 >;
			clock-names = "apb_pclk";

			port {

				endpoint {
					slave-mode;
					remote-endpoint = < 0xd1 >;
					linux,phandle = < 0xca >;
					phandle = < 0xca >;
				};
			};
		};

		debug@12C10000 {
			compatible = "arm,coresight-cpu-debug\0arm,primecell";
			reg = < 0x12c10000 0x1000 >;
			clocks = < 0x18 >;
			clock-names = "apb_pclk";
			cpu = < 0x02 >;
		};

		debug@12D10000 {
			compatible = "arm,coresight-cpu-debug\0arm,primecell";
			reg = < 0x12d10000 0x1000 >;
			clocks = < 0x18 >;
			clock-names = "apb_pclk";
			cpu = < 0x03 >;
		};

		debug@12E10000 {
			compatible = "arm,coresight-cpu-debug\0arm,primecell";
			reg = < 0x12e10000 0x1000 >;
			clocks = < 0x18 >;
			clock-names = "apb_pclk";
			cpu = < 0x04 >;
		};

		debug@12F10000 {
			compatible = "arm,coresight-cpu-debug\0arm,primecell";
			reg = < 0x12f10000 0x1000 >;
			clocks = < 0x18 >;
			clock-names = "apb_pclk";
			cpu = < 0x05 >;
		};

		debug@13410000 {
			compatible = "arm,coresight-cpu-debug\0arm,primecell";
			reg = < 0x13410000 0x1000 >;
			clocks = < 0x18 >;
			clock-names = "apb_pclk";
			cpu = < 0x06 >;
		};

		debug@13510000 {
			compatible = "arm,coresight-cpu-debug\0arm,primecell";
			reg = < 0x13510000 0x1000 >;
			clocks = < 0x18 >;
			clock-names = "apb_pclk";
			cpu = < 0x07 >;
		};

		debug@13610000 {
			compatible = "arm,coresight-cpu-debug\0arm,primecell";
			reg = < 0x13610000 0x1000 >;
			clocks = < 0x18 >;
			clock-names = "apb_pclk";
			cpu = < 0x08 >;
		};

		debug@13710000 {
			compatible = "arm,coresight-cpu-debug\0arm,primecell";
			reg = < 0x13710000 0x1000 >;
			clocks = < 0x18 >;
			clock-names = "apb_pclk";
			cpu = < 0x09 >;
		};

		debug@13810000 {
			compatible = "arm,coresight-cpu-debug\0arm,primecell";
			reg = < 0x13810000 0x1000 >;
			clocks = < 0x18 >;
			clock-names = "apb_pclk";
			cpu = < 0x0a >;
		};

		debug@13910000 {
			compatible = "arm,coresight-cpu-debug\0arm,primecell";
			reg = < 0x13910000 0x1000 >;
			clocks = < 0x18 >;
			clock-names = "apb_pclk";
			cpu = < 0x0b >;
		};

		debug@13A10000 {
			compatible = "arm,coresight-cpu-debug\0arm,primecell";
			reg = < 0x13a10000 0x1000 >;
			clocks = < 0x18 >;
			clock-names = "apb_pclk";
			cpu = < 0x0c >;
		};

		debug@13B10000 {
			compatible = "arm,coresight-cpu-debug\0arm,primecell";
			reg = < 0x13b10000 0x1000 >;
			clocks = < 0x18 >;
			clock-names = "apb_pclk";
			cpu = < 0x0d >;
		};

		etm@12C40000 {
			compatible = "arm,coresight-etm4x\0arm,primecell";
			reg = < 0x12c40000 0x1000 >;
			clocks = < 0x18 >;
			clock-names = "apb_pclk";
			cpu = < 0x02 >;

			port {

				endpoint {
					remote-endpoint = < 0xd2 >;
					linux,phandle = < 0xb8 >;
					phandle = < 0xb8 >;
				};
			};
		};

		etm@12D40000 {
			compatible = "arm,coresight-etm4x\0arm,primecell";
			reg = < 0x12d40000 0x1000 >;
			clocks = < 0x18 >;
			clock-names = "apb_pclk";
			cpu = < 0x03 >;

			port {

				endpoint {
					remote-endpoint = < 0xd3 >;
					linux,phandle = < 0xb9 >;
					phandle = < 0xb9 >;
				};
			};
		};

		etm@12E40000 {
			compatible = "arm,coresight-etm4x\0arm,primecell";
			reg = < 0x12e40000 0x1000 >;
			clocks = < 0x18 >;
			clock-names = "apb_pclk";
			cpu = < 0x04 >;

			port {

				endpoint {
					remote-endpoint = < 0xd4 >;
					linux,phandle = < 0xba >;
					phandle = < 0xba >;
				};
			};
		};

		etm@12F40000 {
			compatible = "arm,coresight-etm4x\0arm,primecell";
			reg = < 0x12f40000 0x1000 >;
			clocks = < 0x18 >;
			clock-names = "apb_pclk";
			cpu = < 0x05 >;

			port {

				endpoint {
					remote-endpoint = < 0xd5 >;
					linux,phandle = < 0xbb >;
					phandle = < 0xbb >;
				};
			};
		};

		etm@13440000 {
			compatible = "arm,coresight-etm4x\0arm,primecell";
			reg = < 0x13440000 0x1000 >;
			clocks = < 0x18 >;
			clock-names = "apb_pclk";
			cpu = < 0x06 >;

			port {

				endpoint {
					remote-endpoint = < 0xd6 >;
					linux,phandle = < 0xbd >;
					phandle = < 0xbd >;
				};
			};
		};

		etm@13540000 {
			compatible = "arm,coresight-etm4x\0arm,primecell";
			reg = < 0x13540000 0x1000 >;
			clocks = < 0x18 >;
			clock-names = "apb_pclk";
			cpu = < 0x07 >;

			port {

				endpoint {
					remote-endpoint = < 0xd7 >;
					linux,phandle = < 0xbe >;
					phandle = < 0xbe >;
				};
			};
		};

		etm@13640000 {
			compatible = "arm,coresight-etm4x\0arm,primecell";
			reg = < 0x13640000 0x1000 >;
			clocks = < 0x18 >;
			clock-names = "apb_pclk";
			cpu = < 0x08 >;

			port {

				endpoint {
					remote-endpoint = < 0xd8 >;
					linux,phandle = < 0xbf >;
					phandle = < 0xbf >;
				};
			};
		};

		etm@13740000 {
			compatible = "arm,coresight-etm4x\0arm,primecell";
			reg = < 0x13740000 0x1000 >;
			clocks = < 0x18 >;
			clock-names = "apb_pclk";
			cpu = < 0x09 >;

			port {

				endpoint {
					remote-endpoint = < 0xd9 >;
					linux,phandle = < 0xc0 >;
					phandle = < 0xc0 >;
				};
			};
		};

		etm@13840000 {
			compatible = "arm,coresight-etm4x\0arm,primecell";
			reg = < 0x13840000 0x1000 >;
			clocks = < 0x18 >;
			clock-names = "apb_pclk";
			cpu = < 0x0a >;

			port {

				endpoint {
					remote-endpoint = < 0xda >;
					linux,phandle = < 0xc2 >;
					phandle = < 0xc2 >;
				};
			};
		};

		etm@13940000 {
			compatible = "arm,coresight-etm4x\0arm,primecell";
			reg = < 0x13940000 0x1000 >;
			clocks = < 0x18 >;
			clock-names = "apb_pclk";
			cpu = < 0x0b >;

			port {

				endpoint {
					remote-endpoint = < 0xdb >;
					linux,phandle = < 0xc3 >;
					phandle = < 0xc3 >;
				};
			};
		};

		etm@13A40000 {
			compatible = "arm,coresight-etm4x\0arm,primecell";
			reg = < 0x13a40000 0x1000 >;
			clocks = < 0x18 >;
			clock-names = "apb_pclk";
			cpu = < 0x0c >;

			port {

				endpoint {
					remote-endpoint = < 0xdc >;
					linux,phandle = < 0xc4 >;
					phandle = < 0xc4 >;
				};
			};
		};

		etm@13B40000 {
			compatible = "arm,coresight-etm4x\0arm,primecell";
			reg = < 0x13b40000 0x1000 >;
			clocks = < 0x18 >;
			clock-names = "apb_pclk";
			cpu = < 0x0d >;

			port {

				endpoint {
					remote-endpoint = < 0xdd >;
					linux,phandle = < 0xc5 >;
					phandle = < 0xc5 >;
				};
			};
		};

		tmu@10180000 {
			compatible = "turbo,trav-tmu";
			reg = < 0x10180000 0x800 >;
			interrupts = < 0x00 0x1da 0x00 >;
			clocks = < 0x14 0x08 >;
			clock-names = "tmu_apbif";
			remote_sensors = < 0x07 >;
			tmu_valid_probe = < 0xff >;
			tmu_name = "TMU_CPU0";
			#thermal-sensor-cells = < 0x00 >;
			samsung,tmu_gain = < 0x00 >;
			samsung,tmu_reference_voltage = < 0x00 >;
			samsung,tmu_noise_cancel_mode = < 0x04 >;
			samsung,tmu_efuse_value = < 0x64 >;
			samsung,tmu_min_efuse_value = < 0x0f >;
			samsung,tmu_max_efuse_value = < 0x64 >;
			samsung,tmu_first_point_trim = < 0x19 >;
			samsung,tmu_second_point_trim = < 0x55 >;
			samsung,tmu_default_temp_offset = < 0x32 >;
			samsung,tmu_cal_type = < 0x00 >;
			status = "disabled";
		};

		tmu@10184000 {
			compatible = "turbo,trav-tmu";
			reg = < 0x10184000 0x800 >;
			interrupts = < 0x00 0x1db 0x00 >;
			clocks = < 0x14 0x08 >;
			clock-names = "tmu_apbif";
			remote_sensors = < 0x04 >;
			tmu_valid_probe = < 0x1f >;
			tmu_name = "TMU_CPU2";
			#thermal-sensor-cells = < 0x00 >;
			samsung,tmu_gain = < 0x00 >;
			samsung,tmu_reference_voltage = < 0x00 >;
			samsung,tmu_noise_cancel_mode = < 0x04 >;
			samsung,tmu_efuse_value = < 0x64 >;
			samsung,tmu_min_efuse_value = < 0x0f >;
			samsung,tmu_max_efuse_value = < 0x64 >;
			samsung,tmu_first_point_trim = < 0x19 >;
			samsung,tmu_second_point_trim = < 0x55 >;
			samsung,tmu_default_temp_offset = < 0x32 >;
			samsung,tmu_cal_type = < 0x00 >;
			status = "disabled";
		};

		tmu@10188000 {
			compatible = "turbo,trav-tmu";
			reg = < 0x10188000 0x800 >;
			interrupts = < 0x00 0x1dc 0x00 >;
			clocks = < 0x14 0x08 >;
			clock-names = "tmu_apbif";
			remote_sensors = < 0x04 >;
			tmu_valid_probe = < 0x1f >;
			tmu_name = "TMU_GT";
			#thermal-sensor-cells = < 0x00 >;
			samsung,tmu_gain = < 0x00 >;
			samsung,tmu_reference_voltage = < 0x00 >;
			samsung,tmu_noise_cancel_mode = < 0x04 >;
			samsung,tmu_efuse_value = < 0x64 >;
			samsung,tmu_min_efuse_value = < 0x0f >;
			samsung,tmu_max_efuse_value = < 0x64 >;
			samsung,tmu_first_point_trim = < 0x19 >;
			samsung,tmu_second_point_trim = < 0x55 >;
			samsung,tmu_default_temp_offset = < 0x32 >;
			samsung,tmu_cal_type = < 0x00 >;
			status = "disabled";
		};

		tmu@1018C000 {
			compatible = "turbo,trav-tmu";
			reg = < 0x1018c000 0x800 >;
			interrupts = < 0x00 0x1dd 0x00 >;
			clocks = < 0x14 0x08 >;
			clock-names = "tmu_apbif";
			remote_sensors = < 0x00 >;
			tmu_valid_probe = < 0x01 >;
			tmu_name = "TMU_TOP";
			#thermal-sensor-cells = < 0x00 >;
			samsung,tmu_gain = < 0x00 >;
			samsung,tmu_reference_voltage = < 0x00 >;
			samsung,tmu_noise_cancel_mode = < 0x04 >;
			samsung,tmu_efuse_value = < 0x64 >;
			samsung,tmu_min_efuse_value = < 0x0f >;
			samsung,tmu_max_efuse_value = < 0x64 >;
			samsung,tmu_first_point_trim = < 0x19 >;
			samsung,tmu_second_point_trim = < 0x55 >;
			samsung,tmu_default_temp_offset = < 0x32 >;
			samsung,tmu_cal_type = < 0x00 >;
			status = "disabled";
		};

		tmu@10190000 {
			compatible = "turbo,trav-tmu";
			reg = < 0x10190000 0x800 >;
			interrupts = < 0x00 0x1de 0x00 >;
			clocks = < 0x14 0x08 >;
			clock-names = "tmu_apbif";
			remote_sensors = < 0x02 >;
			tmu_valid_probe = < 0x07 >;
			tmu_name = "TMU_GPU";
			#thermal-sensor-cells = < 0x00 >;
			samsung,tmu_gain = < 0x00 >;
			samsung,tmu_reference_voltage = < 0x00 >;
			samsung,tmu_noise_cancel_mode = < 0x04 >;
			samsung,tmu_efuse_value = < 0x64 >;
			samsung,tmu_min_efuse_value = < 0x0f >;
			samsung,tmu_max_efuse_value = < 0x64 >;
			samsung,tmu_first_point_trim = < 0x19 >;
			samsung,tmu_second_point_trim = < 0x55 >;
			samsung,tmu_default_temp_offset = < 0x32 >;
			samsung,tmu_cal_type = < 0x00 >;
			status = "disabled";
		};

		thermal-zones {

				cpu-thermal {
				polling-delay-passive = < 0x64 >;
				polling-delay = < 0x3e8 >;
				thermal-sensors = < 0xde 0x16 >;

				trips {

					cpu-alert-0 {
						temperature = < 0x186a0 >;
						hysteresis = < 0x3e8 >;
						type = "passive";
						linux,phandle = < 0xdf >;
						phandle = < 0xdf >;
					};

					cpu-alert-1 {
						temperature = < 0x18e70 >;
						hysteresis = < 0x3e8 >;
						type = "passive";
						linux,phandle = < 0xe0 >;
						phandle = < 0xe0 >;
					};

					cpu-crit-0 {
						temperature = < 0x19a28 >;
						hysteresis = < 0x00 >;
						type = "critical";
					};
				};

				cooling-maps {

					map0 {
						trip = < 0xdf >;
						cooling-device = < 0x02 0x01 0x01 >;
					};

					map1 {
						trip = < 0xe0 >;
						cooling-device = < 0x02 0x02 0x02 >;
					};
				};
			};

			trip0-thermal {
				polling-delay-passive = < 0x64 >;
				polling-delay = < 0x3e8 >;
				thermal-sensors = < 0xde 0x17 >;

				trips {

					trip0-alert-0 {
						temperature = < 0x186a0 >;
						hysteresis = < 0x3e8 >;
						type = "passive";
						linux,phandle = < 0xe1 >;
						phandle = < 0xe1 >;
					};

					trip0-alert-1 {
						temperature = < 0x18e70 >;
						hysteresis = < 0x3e8 >;
						type = "passive";
						linux,phandle = < 0xe3 >;
						phandle = < 0xe3 >;
					};

					trip0-alert-2 {
						temperature = < 0x19640 >;
						hysteresis = < 0x3e8 >;
						type = "passive";
						linux,phandle = < 0xe4 >;
						phandle = < 0xe4 >;
					};

					trip0-crit-0 {
						temperature = < 0x100590 >;
						hysteresis = < 0x00 >;
						type = "critical";
					};
				};

				cooling-maps {

					map0 {
						trip = < 0xe1 >;
						cooling-device = < 0xe2 0x01 0x01 >;
					};

					map1 {
						trip = < 0xe3 >;
						cooling-device = < 0xe2 0x02 0x02 >;
					};

					map2 {
						trip = < 0xe4 >;
						cooling-device = < 0xe2 0x03 0x03 >;
					};
				};
			};

			trip1-thermal {
				polling-delay-passive = < 0x64 >;
				polling-delay = < 0x3e8 >;
				thermal-sensors = < 0xde 0x18 >;

				trips {

					trip1-alert-0 {
						temperature = < 0x186a0 >;
						hysteresis = < 0x3e8 >;
						type = "passive";
						linux,phandle = < 0xe5 >;
						phandle = < 0xe5 >;
					};

					trip1-alert-1 {
						temperature = < 0x18e70 >;
						hysteresis = < 0x3e8 >;
						type = "passive";
						linux,phandle = < 0xe7 >;
						phandle = < 0xe7 >;
					};

					trip1-alert-2 {
						temperature = < 0x19640 >;
						hysteresis = < 0x3e8 >;
						type = "passive";
						linux,phandle = < 0xe8 >;
						phandle = < 0xe8 >;
					};

					trip1-crit-0 {
						temperature = < 0x100590 >;
						hysteresis = < 0x00 >;
						type = "critical";
					};
				};

				cooling-maps {

					map0 {
						trip = < 0xe5 >;
						cooling-device = < 0xe6 0x01 0x01 >;
					};

					map1 {
						trip = < 0xe7 >;
						cooling-device = < 0xe6 0x02 0x02 >;
					};

					map2 {
						trip = < 0xe8 >;
						cooling-device = < 0xe6 0x03 0x03 >;
					};
				};
			};

			gpu-thermal {
				polling-delay-passive = < 0x64 >;
				polling-delay = < 0x3e8 >;
				thermal-sensors = < 0xde 0x19 >;

				trips {

					gpu-crit-0 {
						temperature = < 0x19a28 >;
						hysteresis = < 0x00 >;
						type = "critical";
					};
				};
			};

			other-thermal {
				polling-delay-passive = < 0x64 >;
				polling-delay = < 0x3e8 >;
				thermal-sensors = < 0xde 0x1a >;

				trips {

					other-crit-0 {
						temperature = < 0x19a28 >;
						hysteresis = < 0x00 >;
						type = "critical";
					};
				};
			};
		};

		tripmem@1c0000000 {
			compatible = "tesla,tripmem";
			memory-region = < 0xe9 >;
			status = "okay";
		};

		tripmem@1a0000000 {
			compatible = "tesla,tripmem";
			memory-region = < 0xea >;
			ecc;
			status = "okay";
		};

		tdm@140E0000 {
			compatible = "samsung,exynos7-i2s";
			reg = < 0x140e0000 0x100 >;
			interrupts = < 0x00 0xce 0x04 >;
			dmas = < 0x29 0x0e 0x29 0x0d >;
			dma-names = "tx\0rx";
			#address-cells = < 0x01 >;
			#size-cells = < 0x00 >;
			clocks = < 0x16 0x28 0x16 0x0f >;
			clock-names = "i2s_opclk0\0iis";
			pinctrl-names = "default";
			pinctrl-0 = < 0xeb >;
			samsung,use-opclk;
			linux,phandle = < 0xf6 >;
			phandle = < 0xf6 >;

			i2s-sec {
				dmas = < 0x29 0x0c >;
				dma-names = "tx-sec";
			};
		};

		isp@0x12200000 {
			compatible = "arm,mali-c71";
			reg = < 0x12200000 0x20000 >;
			reg-names = "isp_reg";
			interrupts = < 0x00 0x15b 0x04 0x00 0x15c 0x04 0x00 0x15d 0x04 0x00 0x15e 0x04 0x00 0x15f 0x04 >;
			iommus = < 0x67 0x800 0x00 0x67 0xc00 0x00 >;
			status = "okay";
		};

		trip@BFFE000 {
			compatible = "tesla,trip";
			reg = < 0xbffe000 0x2000 0x8000000 0x2000000 >;
			interrupts = < 0x00 0x16 0x04 0x00 0x17 0x04 0x00 0x18 0x04 0x00 0x19 0x04 0x00 0x1a 0x04 0x00 0x1b 0x04 0x00 0x1c 0x04 0x00 0x1d 0x04 0x00 0x1e 0x04 0x00 0x1f 0x04 0x00 0x20 0x04 0x00 0x21 0x04 0x00 0x22 0x04 0x00 0x23 0x04 0x00 0x24 0x04 0x00 0x25 0x04 0x00 0x26 0x04 0x00 0x27 0x04 >;
			iommus = < 0xec 0x00 0x00 >;
			#clock-cells = < 0x01 >;
			clocks = < 0xed 0x01 0xed 0x02 0xed 0x03 0xed 0x04 >;
			clock-names = "fout_pll_trip\0mout_trip_pll\0mout_trip_switch_mux\0mout_trip_switch_pll_mux";
			operating-points-v2 = < 0xee >;
			trip-supply = < 0xef >;
			#cooling-cells = < 0x02 >;
			status = "okay";
			firmware = "trip0.fw";
			linux,phandle = < 0xe2 >;
			phandle = < 0xe2 >;
		};

		trip@FFFE000 {
			compatible = "tesla,trip";
			reg = < 0xfffe000 0x2000 0xc000000 0x2000000 >;
			interrupts = < 0x00 0x2b 0x04 0x00 0x2c 0x04 0x00 0x2d 0x04 0x00 0x2e 0x04 0x00 0x2f 0x04 0x00 0x30 0x04 0x00 0x31 0x04 0x00 0x32 0x04 0x00 0x33 0x04 0x00 0x34 0x04 0x00 0x35 0x04 0x00 0x36 0x04 0x00 0x37 0x04 0x00 0x38 0x04 0x00 0x39 0x04 0x00 0x3a 0x04 0x00 0x3b 0x04 0x00 0x3c 0x04 >;
			iommus = < 0xf0 0x00 0x00 >;
			#clock-cells = < 0x01 >;
			clocks = < 0xf1 0x01 0xf1 0x02 0xf1 0x03 0xf1 0x04 >;
			clock-names = "fout_pll_trip\0mout_trip_pll\0mout_trip_switch_mux\0mout_trip_switch_pll_mux";
			operating-points-v2 = < 0xf2 >;
			trip-supply = < 0xef >;
			#cooling-cells = < 0x02 >;
			status = "okay";
			firmware = "trip1.fw";
			linux,phandle = < 0xe6 >;
			phandle = < 0xe6 >;
		};
	};

	firmware {

		tesla {
			board_version = "TURBO_BOARD_VERSION_TOKEN_STRING";
			turbo_a_b = "TURBO_A_B_TOKEN_STRING";
			otp_chip_id = "TURBO_OTP_CHIP_ID_32_TOKEN_STRING";
			soc_id = "TURBO_SOC_ID_TOKEN_STRING";
			bootfrom = "BOOTFROM_TOKEN_STRING";
			a72bl1_coreboot_version = "A72BL1_COREBOOT_VERSION_TOKEN_STRING";
			a72bootblock_coreboot_version = "A72BOOTBLOCK_COREBOOT_VERSION_TOKEN_STRING";
			coreboot_version = "COREBOOT_VERSION_TOKEN_STRING";
			coreboot_extra_version = "COREBOOT_EXTRA_VERSION_TOKEN_STRING";
			coreboot_build = "COREBOOT_BUILD_TOKEN_LONG_STRING";
			board_pcba_version = "BOARD_PCBA_VERSION_TOKEN_STRING";
			scsbl1_build_version = "SCSBL1_BUILD_VERSION_TOKEN_STRING";
			scsbl1_build_version_string = "SCSBL1_BUILD_VERSION_STRING_TOKEN_STRING_1234567890_1234567890_1234567";
			scsbl1_build_git_hash = "SCSBL1_BUILD_GIT_HASH_TOKEN_STRING_1234567890";
			scsbl2_build_version = "SCSBL2_BUILD_VERSION_TOKEN_STRING";
			scsbl2_build_version_string = "SCSBL2_BUILD_VERSION_STRING_TOKEN_STRING_1234567890_1234567890_1234567";
			scsbl2_build_git_hash = "SCSBL2_BUILD_GIT_HASH_TOKEN_STRING_1234567890";
			sms_build_version = "SMS_BUILD_VERSION_TOKEN_STRING";
			sms_build_git_hash = "SMS_BUILD_GIT_HASH_TOKEN_STRING_1234567890";
			a72bl1_build_version = "A72BL1_BUILD_VERSION_TOKEN_STRING";
			a72bootblock_build_version = "A72BOOTBLOCK_BUILD_VERSION_TOKEN_STRING";
			a72coreboot_build_version = "A72COREBOOT_BUILD_VERSION_TOKEN_STRING";
			ddr_vendor = "DDR_VENDOR_TOKEN_STRING";
		};
	};

	chosen {
		linux,stdout-path = "/soc/serial@14180000";
		linux,initrd-start = < 0xe0000000 >;
		linux,initrd-end = < 0xe0000000 >;
		bootargs = "console=ttySAC0,115200n8 clk_ignore_unused earlycon=exynos4210,0x14180000 max_loop=1 bootfrom=ua root=PARTUUID=DEV_00112233445566778899AABBCCDDEEFF";
	};

	memory@80000000 {
		device_type = "memory";
		reg = < 0x00 0x80000000 0x01 0xc0000000 >;
	};

	regulator-usb30 {
		compatible = "regulator-fixed";
		regulator-name = "VBUS_5V";
		regulator-min-microvolt = < 0x4c4b40 >;
		regulator-max-microvolt = < 0x4c4b40 >;
		gpio = < 0xf3 0x01 0x00 >;
		pinctrl-names = "default";
		pinctrl-0 = < 0xf4 >;
		enable-active-high;
		linux,phandle = < 0x5d >;
		phandle = < 0x5d >;
	};

	regulator-gps-ant {
		compatible = "regulator-fixed";
		regulator-name = "gps-ant";
		regulator-min-microvolt = < 0x4c4b40 >;
		regulator-max-microvolt = < 0x4c4b40 >;
		gpio = < 0xf5 0x04 0x00 >;
		enable-active-high;
		regulator-boot-on;
		regulator-always-on;
	};

	sound {
		compatible = "samsung,trav-audio";
		samsung,audio-cpu = < 0xf6 >;
		samsung,audio-codec = < 0xf7 >;
		samsung,i2s-tx-fifo = < 0x140e0010 >;
		samsung,i2s-rx-fifo = < 0x140e0014 >;
		samsung,i2s-tx-s-fifo = < 0x140e001c >;
		mute-gpios = < 0x59 0x04 0x01 0xf5 0x01 0x00 >;
		status = "okay";
	};

	pwm-fan {
		compatible = "pwm-fan";
		pwms = < 0xf8 0x01 0x9c40 0x01 >;
		cooling-min-state = < 0x00 >;
		cooling-max-state = < 0x09 >;
		#cooling-cells = < 0x02 >;
		cooling-levels = < 0x3c 0x50 0x64 0x78 0x8c 0xa0 0xb4 0xc8 0xdc 0xf0 >;
		status = "okay";
	};

	tachometer {
		compatible = "gpio-tachometer";
		gpio = < 0x59 0x05 0x00 >;
		pulses-per-rev = < 0x02 >;
		status = "okay";
	};

	pps {
		compatible = "pps-gpio";
		gpios = < 0x2d 0x04 0x00 >;
		status = "okay";
	};
};