// Copyright (C) 1991-2009 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors.  Please refer to the
// applicable agreement for further details.

// PROGRAM      "Quartus II"
// VERSION      "Version 9.0 Build 132 02/25/2009 SJ Full Version"
// CREATED ON   "Mon Mar 04 19:59:55 2019"

module test1(
    B,
    A,
    GN1,
    C10,
    C11,
    C12,
    C13,
    C20,
    C21,
    C22,
    C23,
    GN2,
    Y2,
    Y1
);


input   B;
input   A;
input   GN1;
input   C10;
input   C11;
input   C12;
input   C13;
input   C20;
input   C21;
input   C22;
input   C23;
input   GN2;
output  Y2;
output  Y1;

wire    SYNTHESIZED_WIRE_20;
wire    SYNTHESIZED_WIRE_21;
wire    SYNTHESIZED_WIRE_6;
wire    SYNTHESIZED_WIRE_7;
wire    SYNTHESIZED_WIRE_8;
wire    SYNTHESIZED_WIRE_9;
wire    SYNTHESIZED_WIRE_10;
wire    SYNTHESIZED_WIRE_11;
wire    SYNTHESIZED_WIRE_14;
wire    SYNTHESIZED_WIRE_15;
wire    SYNTHESIZED_WIRE_16;
wire    SYNTHESIZED_WIRE_17;
wire    SYNTHESIZED_WIRE_18;
wire    SYNTHESIZED_WIRE_19;




assign  SYNTHESIZED_WIRE_21 =  ~A;

assign  SYNTHESIZED_WIRE_20 =  ~B;

assign  SYNTHESIZED_WIRE_6 = SYNTHESIZED_WIRE_20 & SYNTHESIZED_WIRE_21 & C20;

assign  SYNTHESIZED_WIRE_7 = SYNTHESIZED_WIRE_20 & A & C21;

assign  SYNTHESIZED_WIRE_8 = B & SYNTHESIZED_WIRE_21 & C22;

assign  SYNTHESIZED_WIRE_14 = SYNTHESIZED_WIRE_20 & SYNTHESIZED_WIRE_21 & C10;

assign  SYNTHESIZED_WIRE_9 = B & A & C23;

assign  SYNTHESIZED_WIRE_10 = SYNTHESIZED_WIRE_6 | SYNTHESIZED_WIRE_7 | SYNTHESIZED_WIRE_8 | SYNTHESIZED_WIRE_9;

assign  Y2 = SYNTHESIZED_WIRE_11 ? SYNTHESIZED_WIRE_10 : 1'bz;

assign  SYNTHESIZED_WIRE_19 =  ~GN1;

assign  SYNTHESIZED_WIRE_15 = SYNTHESIZED_WIRE_20 & A & C11;

assign  SYNTHESIZED_WIRE_11 =  ~GN2;

assign  SYNTHESIZED_WIRE_16 = B & SYNTHESIZED_WIRE_21 & C12;

assign  SYNTHESIZED_WIRE_17 = B & A & C13;

assign  SYNTHESIZED_WIRE_18 = SYNTHESIZED_WIRE_14 | SYNTHESIZED_WIRE_15 | SYNTHESIZED_WIRE_16 | SYNTHESIZED_WIRE_17;

assign  Y1 = SYNTHESIZED_WIRE_19 ? SYNTHESIZED_WIRE_18 : 1'bz;


endmodule