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- module ba(
- output reg o, // found output: 0 - not found, 1 - found
- input i, // char input: 0 - 'a', 1 - 'b'
- input clk); // clock input
- //TODO implementarea functionarii
- reg[1:0] state = 0, next_state = 0;
- always@(posedge clk) begin
- state <= next_state;
- end
- always@(*) begin
- o = 0;
- case (state)
- 0: if(i == 1) begin
- next_state = 1;
- o = 0;
- end
- else begin
- next_state = 2;
- o = 0;
- end
- 1: if(i == 1) begin
- next_state = 3;
- o = 1;
- end
- else begin
- next_state = 2;
- o = 0;
- end
- 2: if(i == 1) begin
- next_state = 1;
- o = 0;
- end
- else begin
- next_state = 2;
- o = 0;
- end
- 3: if(i == 1) begin
- next_state = 1;
- o = 0;
- end
- else begin
- next_state = 2;
- o = 0;
- end
- endcase
- end
- endmodule
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