module ram();

  reg [6:0] adrs;
  reg [15:0] content;
  reg _ce, _we, _oe;
  wire [15:0] data;
  assign data = ~_ce & ~_we & _oe ? content : 8'hz;
  ram128x16 u1(adrs, data, _ce,_we,_oe);
  initial begin
    $monitor ("%4d: adrs = %h _ce + %b _we = %b _oe = %b data =%h", $time, adrs, _ce, _we, _oe, data);

    adrs = 7'd0;
    content = 16'd0;
    _ce = 1'b0; _we = 1'b0; _oe = 1'b1;
    #100
    _ce = 1'b1; _we = 1'b1; _oe = 1'b1;
	#500
    adrs = 7'b011111;
    content = 16'hFFFF;
    _ce = 1'b0; _we = 1'b0; _oe = 1'b1;
    #100
    _ce = 1'b1; _we = 1'b1; _oe = 1'b1;
	#400
    adrs = 7'b100000;
    content = 16'd1514;
    _ce = 1'b0; _we = 1'b0; _oe = 1'b1;
    #100
    _ce = 1'b1; _we = 1'b1; _oe = 1'b1;
	#400
    adrs = 7'b110000;
    content = 16'd1260;
    _ce = 1'b0; _we = 1'b0; _oe = 1'b1;
    #100
    _ce = 1'b1; _we = 1'b1; _oe = 1'b1;
	#400

    //read

    adrs = 7'b000000;
    _ce = 1'b0; _we = 1'b1; _oe = 1'b0;
    #100
    _ce = 1'b1; _we = 1'b1; _oe = 1'b1;
	#500
    adrs = 7'b011111;
    _ce = 1'b0; _we = 1'b1; _oe = 1'b0;
    #100
    _ce = 1'b1; _we = 1'b1; _oe = 1'b1;
	#400
    adrs = 7'b100000;
    _ce = 1'b0; _we = 1'b1; _oe = 1'b0;
    #100
    _ce = 1'b1; _we = 1'b1; _oe = 1'b1;
	#400
    adrs = 7'b110000;
    _ce = 1'b0; _we = 1'b1; _oe = 1'b0;
    #100
    _ce = 1'b1; _we = 1'b1; _oe = 1'b1;
	#400


	$finish;



end


endmodule