----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date:    01:53:54 12/04/2016
-- Design Name:
-- Module Name:    rom16x8 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity rom16x8 is
	port(
		adr : in std_logic_vector(3 downto 0);
		cs : in std_logic;
		data : out std_logic_vector(7 downto 0)
	);
end rom16x8;

architecture Behavioral of rom16x8 is
begin
	data <= "0000"&adr when cs = '1' else
				"ZZZZZZZZ";
end Behavioral;








----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date:    01:41:23 12/04/2016
-- Design Name:
-- Module Name:    sram8x8 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity sram8x8 is
	port(
		adr : in std_logic_vector(2 downto 0);
		we, oe, cs : in std_logic;
		data : inout std_logic_vector(7 downto 0)
	);
end sram8x8;

architecture Behavioral of sram8x8 is
type sram_array is array (0 to 7) of std_logic_vector(7 downto 0);
signal sram : sram_array;
begin
	process(we, oe, cs, adr, data, sram)
		begin
			if(cs = '1') then
				if(we = '1' and oe = '0') then
					sram(conv_integer(adr)) <= data;
				elsif(we = '0' and oe = '1') then
					data <= sram(conv_integer(adr));
				else
					data <= (others => 'Z');
				end if;
			else
				data <= (others => 'Z');
			end if;
		end process;
end Behavioral;










----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date:    02:00:02 12/04/2016
-- Design Name:
-- Module Name:    ured - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity ured is
	port(
				start , clk: in std_logic
	);
end ured;

architecture Behavioral of ured is
signal adr1 : std_logic_vector(3 downto 0) := "0000";
signal adr2 : std_logic_vector(2 downto 0) := "000";
signal data1, data2, sum: std_logic_vector(7 downto 0) := (others => '0');
signal we, cs1, cs2 : std_logic := '1';
signal oe : std_logic := '0';
type sram_array is array (0 to 7) of std_logic_vector(7 downto 0);
signal sram : sram_array;
begin
	process(data1, sum, adr1, adr2, start, clk)
		variable cnt : integer range 0 to 2;
		begin
			if(start = '1' and rising_edge(clk)) then
					if(cnt = 2) then
						data2 <= sum;
						adr2 <= adr2 + 1;
						sum <= "00000000";
						cnt := 0;
					end if;
					sum <= sum + data1;
					adr1 <= adr1 + 1;
					cnt := cnt + 1;
			end if;
	end process;
	rom:process(adr1, cs1)
		begin
			if cs1 = '1' then
				data1 <= "0000"&adr1;
			end if;
		end process rom;
	ram:process(we, oe, cs2, adr2, data2, sram)
		begin
			if(cs2 = '1') then
				if(we = '1' and oe = '0') then
					sram(conv_integer(adr2)) <= data2;
				elsif(we = '0' and oe = '1') then
					data2 <= sram(conv_integer(adr2));
				else
					data2 <= (others => 'Z');
				end if;
			else
				data2 <= (others => 'Z');
			end if;
		end process ram;
end Behavioral;