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Zoinkity

Partial dASM of NTSC PIFROM Code

Zoinkity
Oct 31st, 2015
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  1. BFC007E4: device state flags
  2. 00080000 S3: osRomType (True boots from IPL, not cartridge)
  3. 00040000 S7: osVersion
  4. 00020000 S5: osResetType
  5. 0000FF00 S6: CIC seed value
  6. 000000FF mirror of CIC seed value, unread
  7. osTvType is set manually by PIF to S4
  8.  
  9. BFC00000 PIF bootrom (NTSC)
  10. LUI T5,BFC0
  11. LW T0,07FC (T5) ;T0=BFC007FC: PIF status byte
  12. ADDIU T5,T5,07C0
  13. ANDI T0,T0,0080
  14. BNEL T0,R0,BFC00004 ;loop until ready (0x80 unset)
  15. LUI T5,BFC0
  16. @BFC00018: select cart or IPL source
  17. LW T0,0024 (T5) ;T0=@BFC007E4: device state
  18. LUI T3,B000
  19. SRL S3,T0,0x13
  20. ANDI S3,S3,0001 ;S3 = True if T0 & 0x80000 else False
  21. SRL S7,T0,0x12
  22. BEQ S3,R0,BFC00038 ;If S3 True, use IPL instead of cartridge
  23. ANDI S7,S7,0001 ;S7 = True if S7 & 0x40000 else False
  24. LUI T3,A600
  25. @BFC00038:
  26. SRL S6,T0,0x8
  27. ANDI T2,T0,00FF ;T2 = T0 & 0xFF
  28. SRL S5,T0,0x11
  29. LW T0,003C (T5) ;T0= @BFC007FC: PIF status byte
  30. ADDIU T1,R0,0010
  31. ANDI S6,S6,00FF ;S6 = (T0 & 0xFF00) >> 8: CIC seed
  32. ANDI S5,S5,0001 ;S5 = True if T0 & 0x20000 else False
  33. ADDIU S4,R0,0001 ;S4 = 1: NTSC osTvType
  34. OR T0,T0,T1 ;PIF.status |= 0x10
  35. @BFC0005C: wait until SI status ready
  36. LUI T1,A480
  37. LW T1,0018 (T1) ;T1 = @A4800018: SI.status
  38. ANDI T1,T1,0002
  39. BNEL T1,R0,BFC00060 ;loop while SI I/O busy
  40. LUI T1,A480
  41. @BFC00070: initialize PI domain 1 settings
  42. SW T0,003C (T5) ;update PIF.status
  43. LUI T4,A460
  44. ADDIU T0,R0,00FF
  45. SW T0,0014 (T4) ;latency: 0xFF
  46. SW T0,0018 (T4) ;pulse width: 0xFF
  47. ADDIU T0,R0,000F
  48. SW T0,001C (T4) ;page size: 0xF
  49. ADDIU T0,R0,0003
  50. SW T0,0020 (T4) ;release: 3
  51. @BFC00094: set initial PI domain 1 settings based on ROM header
  52. LW T1,0000 (T3) ;T1 = @ROM: initial PI settings in header
  53. LUI T5,A410
  54. ADDIU T4,T4,0000
  55. ANDI T0,T1,00FF
  56. SW T0,0014 (T4) ;latency: init & 0xFF
  57. SRL T0,T1,0x8
  58. SW T0,0018 (T4) ;pulse width: init >> 8
  59. SRL T0,T1,0x10
  60. SW T0,001C (T4) ;page size: init >> 16
  61. SRL T0,T1,0x14
  62. SW T0,0020 (T4) ;release: init >> 20
  63. @BFC000C0:
  64. LW T7,000C (T5) ;T7 = @A410000C: DP command status
  65. ADDI T0,R0,0FC0
  66. ADDI T3,T3,0040 ;T3 = ROM+40: p->bootstrap code
  67. ANDI T7,T7,0001
  68. BEQ T7,R0,BFC000F0
  69. ADDIU T5,T5,000C
  70. @BFC000D8:
  71. LUI T5,A410
  72. LW T7,000C (T5)
  73. ADDIU T5,T5,000C
  74. ANDI T7,T7,0020
  75. BNEL T7,R0,BFC000DC
  76. LUI T5,A410
  77. @BFC000F0:
  78. LUI T5,A400
  79. ADDIU T5,T5,0000
  80. OR A2,R0,T0
  81. ADDI T5,T5,0040 ;T5 = A4000040
  82. @BFC00100: copy 0xFC0 bytes from bootstrap to A4000040
  83. LW T1,0000 (T3)
  84. ADDI T0,T0,FFFC
  85. ADDI T3,T3,0004
  86. ADDI T5,T5,0004
  87. BNE T0,R0,BFC00100
  88. SW T1,FFFC (T5)
  89. @BFC00118:
  90. LUI T0,6C07
  91. ORI T0,T0,8965 ;T0 = 6C078965
  92. MULTU T2,T0
  93. MFLO A0
  94. ADDIU A0,A0,0001 ;A0 = 0x6C078965 * (seed & 0xFF) + 1
  95. LUI A1,A400
  96. ADDIU A1,A1,0040 ;A1 = A4000040: copy of bootstrap code
  97. BGEZAL R0,BFC00184
  98. NOP
  99. @BFC0013C:
  100. accepts: A0=value, A1=cur word in bootstrap, A2=count
  101. ADDIU SP,SP,FFD0
  102. BNE A1,R0,BFC0014C ;if A1 is 0: A1 = count
  103. SW RA,001C (SP)
  104. OR A1,A2,R0
  105. @BFC0014C:
  106. ADDIU A2,SP,002C
  107. BGEZAL R0,BFC00550 ;(A2, A3) = A0 * A1
  108. ADDIU A3,SP,0028
  109. @BFC00158:
  110. LW A0,0028 (SP)
  111. LW T6,002C (SP)
  112. SUBU V0,T6,A0 ;V0 = target.hi - target.lo
  113. BNE V0,R0,BFC00170
  114. OR V1,V0,R0
  115. OR V1,A0,R0 ;if not V0: return target.lo
  116. @BFC00170: return
  117. LW RA,001C (SP)
  118. ADDIU SP,SP,0030
  119. OR V0,V1,R0
  120. JR RA
  121. NOP
  122.  
  123. BFC00184 calculate checksum for bootstrap
  124. accepts: A0=seed * 0x6C078965, A1=p->bootstrap code
  125. ADDIU SP,SP,FF20
  126. SW RA,003C (SP)
  127. SW S7,0034 (SP)
  128. SW S6,0030 (SP)
  129. SW S5,002C (SP)
  130. SW S4,0028 (SP)
  131. SW S3,0024 (SP)
  132. SW S2,0020 (SP)
  133. SW S1,001C (SP)
  134. SW S0,0018 (SP)
  135. LW T6,0000 (A1) ;T6 = bootstrap[0]
  136. OR V1,R0,R0
  137. ADDIU V1,SP,00B4
  138. ADDIU V0,SP,0074
  139. XOR S0,T6,A0 ;S0 = initial (bootstrap[0] ^ seedword)
  140. @BFC001C0: fill SP+74 - SP+B4 with initial
  141. ADDIU V0,V0,0010
  142. SW S0,FFF4 (V0) ;SP+78 = initial
  143. SW S0,FFF8 (V0) ;SP+7C =initial
  144. SW S0,FFFC (V0) ;SP+80 = initial
  145. BNE V0,V1,BFC001C0
  146. SW S0,FFF0 (V0) ;SP+74 = initial
  147. @BFC001D8
  148. LW S0,0000 (A1) ;S0=bootstrap[0]
  149. OR S1,R0,R0 ;S1 = count
  150. OR S6,A1,R0 ;S6 = p->bootstrap
  151. ADDIU S7,R0,0020
  152. OR S4,S0,R0 ;S4 = bootstrap[0]
  153. LW S0,0000 (S6)
  154. ADDIU S1,S1,0001 ;count+=1
  155. ADDIU T7,R0,03EF
  156. LW S3,0004 (S6) ;S3 = next(bootstrap)
  157. ADDIU S6,S6,0004
  158. SUBU A0,T7,S1 ;A0 = 0x3EF - count
  159. OR A2,S1,R0 ;A2 = count
  160. BGEZAL R0,BFC0013C
  161. OR A1,S0,R0 ;A1 = cur
  162. @BFC00210
  163. LW V1,0074 (SP)
  164. LW A0,0078 (SP) ;A0 = @SP+78: value
  165. OR A1,S0,R0 ;A1 = cur
  166. ADDU V1,V0,V1
  167. SW V1,0074 (SP) ;SP+74 -= V0
  168. BGEZAL R0,BFC0013C
  169. OR A2,S1,R0 ;A2 = count
  170. @BFC0022C
  171. LW T8,007C (SP)
  172. LUI A1,6C07
  173. SW V0,0078 (SP)
  174. XOR T9,T8,S0
  175. SW T9,007C (SP)
  176. ORI A1,A1,8965 ;A1 = 0x6C078965
  177. ADDIU A0,S0,0005
  178. BGEZAL R0,BFC0013C
  179. OR A2,S1,R0
  180. @BFC00250
  181. LW T0,0080 (SP)
  182. SLTU AT,S4,S0
  183. ADDU T1,V0,T0
  184. BEQ AT,R0,BFC0027C
  185. SW T1,0080 (SP)
  186. LW A0,0098 (SP)
  187. OR A1,S0,R0
  188. BGEZAL R0,BFC0013C
  189. OR A2,S1,R0
  190. @BFC00274
  191. BEQ R0,R0,BFC00288
  192. SW V0,0098 (SP)
  193. @BFC0027C
  194. LW T2,0098 (SP)
  195. ADDU T3,T2,S0
  196. SW T3,0098 (SP)
  197. @BFC00288
  198. ANDI V0,S4,001F
  199. LW T6,0084 (SP)
  200. SUBU V1,S7,V0
  201. SLLV T5,S0,V1
  202. SRLV T4,S0,V0
  203. OR S5,T4,T5
  204. SRLV T9,S0,V1
  205. SLLV T8,S0,V0
  206. ADDU T7,T6,S5
  207. SW T7,0084 (SP)
  208. OR A1,T8,T9
  209. LW A0,0090 (SP)
  210. BGEZAL R0,BFC0013C
  211. OR A2,S1,R0
  212. @BFC002C0
  213. LW V1,008C (SP)
  214. SW V0,0090 (SP)
  215. SLTU AT,S0,V1
  216. BEQL AT,R0,BFC002F0
  217. LW T3,0084 (SP)
  218. LW T0,0080 (SP)
  219. ADDU T2,S0,S1
  220. ADDU T1,T0,V1
  221. XOR V1,T1,T2
  222. BEQ R0,R0,BFC002FC
  223. SW V1,008C (SP)
  224. @BFC002EC
  225. LW T3,0084 (SP)
  226. ADDU T4,T3,S0
  227. XOR V1,T4,V1
  228. SW V1,008C (SP)
  229. @BFC002FC
  230. SRL V0,S4,0x1B
  231. LW T7,0088 (SP)
  232. SUBU V1,S7,V0
  233. SRLV T6,S0,V1
  234. SLLV T5,S0,V0
  235. OR S2,T5,T6
  236. SLLV T0,S0,V1
  237. SRLV T9,S0,V0
  238. ADDU T8,T7,S2
  239. SW T8,0088 (SP)
  240. OR A1,T9,T0
  241. LW A0,0094 (SP)
  242. BGEZAL R0,BFC0013C
  243. OR A2,S1,R0
  244. ADDIU AT,R0,03F0
  245. BEQ S1,AT,BFC00420
  246. SW V0,0094 (SP)
  247. LW A0,00B0 (SP)
  248. OR A1,S2,R0
  249. BGEZAL R0,BFC0013C
  250. OR A2,S1,R0
  251. SRL V1,S0,0x1B
  252. SUBU T2,S7,V1
  253. SRLV T3,S3,T2
  254. SLLV T1,S3,V1
  255. OR A1,T1,T3
  256. OR A0,V0,R0
  257. BGEZAL R0,BFC0013C
  258. OR A2,S1,R0
  259. SW V0,00B0 (SP)
  260. LW A0,00AC (SP)
  261. OR A1,S5,R0
  262. BGEZAL R0,BFC0013C
  263. OR A2,S1,R0
  264. ANDI S2,S0,001F
  265. SUBU S4,S7,S2
  266. SLLV T5,S3,S4
  267. SRLV T4,S3,S2
  268. OR A1,T4,T5
  269. OR A0,V0,R0
  270. BGEZAL R0,BFC0013C
  271. OR A2,S1,R0
  272. LW T1,00A8 (SP)
  273. ANDI V1,S3,001F
  274. SRLV T6,S0,S2
  275. SLLV T7,S0,S4
  276. SUBU T9,S7,V1
  277. OR A3,T6,T7
  278. SLLV T0,S3,T9
  279. SRLV T8,S3,V1
  280. LW T5,009C (SP)
  281. OR T2,T8,T0
  282. ADDU T3,T1,A3
  283. ADDU T4,T3,T2
  284. SW V0,00AC (SP)
  285. SW T4,00A8 (SP)
  286. OR A1,S3,R0
  287. OR A2,S1,R0
  288. BGEZAL R0,BFC0013C
  289. ADDU A0,T5,S0
  290. LW T6,00A0 (SP)
  291. SW V0,009C (SP)
  292. OR A1,S3,R0
  293. OR A2,S1,R0
  294. BGEZAL R0,BFC0013C
  295. XOR A0,T6,S0
  296. LW T7,0094 (SP)
  297. LW T8,00A4 (SP)
  298. SW V0,00A0 (SP)
  299. XOR T9,T7,S0
  300. ADDU T0,T9,T8
  301. BEQ R0,R0,BFC001E8
  302. SW T0,00A4 (SP)
  303. @BFC00420
  304. LW V1,0074 (SP)
  305. OR S1,R0,R0
  306. ADDIU S3,SP,0074
  307. ADDIU S5,R0,0010
  308. ADDIU S4,R0,0001
  309. SW V1,0064 (SP)
  310. SW V1,0068 (SP)
  311. SW V1,006C (SP)
  312. SW V1,0070 (SP)
  313. @BFC00444
  314. LW S0,0000 (S3)
  315. LW T5,0064 (SP)
  316. ANDI V0,S0,001F
  317. SUBU T3,S7,V0
  318. SLLV T2,S0,T3
  319. SRLV T1,S0,V0
  320. OR T4,T1,T2
  321. ADDU T6,T5,T4
  322. SLTU AT,S0,T6
  323. BEQ AT,R0,BFC00480
  324. SW T6,0064 (SP)
  325. LW T7,0068 (SP)
  326. ADDU T9,T7,S0
  327. BEQ R0,R0,BFC00494
  328. SW T9,0068 (SP)
  329. @BFC00480
  330. LW A0,0068 (SP)
  331. OR A1,S0,R0
  332. BGEZAL R0,BFC0013C
  333. OR A2,S1,R0
  334. SW V0,0068 (SP)
  335. @BFC00494
  336. ANDI T8,S0,0002
  337. SRL T0,T8,0x1
  338. ANDI S2,S0,0001
  339. BNEL T0,S2,BFC004BC
  340. LW A0,006C (SP)
  341. LW T3,006C (SP)
  342. ADDU T1,T3,S0
  343. BEQ R0,R0,BFC004CC
  344. SW T1,006C (SP)
  345. @BFC004B8
  346. LW A0,006C (SP)
  347. OR A1,S0,R0
  348. BGEZAL R0,BFC0013C
  349. OR A2,S1,R0
  350. SW V0,006C (SP)
  351. @BFC004CC
  352. BNEL S4,S2,BFC004E8
  353. LW A0,0070 (SP)
  354. LW T2,0070 (SP)
  355. XOR T5,T2,S0
  356. BEQ R0,R0,BFC004F8
  357. SW T5,0070 (SP)
  358. @BFC004E4
  359. LW A0,0070 (SP)
  360. OR A1,S0,R0
  361. BGEZAL R0,BFC0013C
  362. OR A2,S1,R0
  363. SW V0,0070 (SP)
  364. @BFC004F8
  365. ADDIU S1,S1,0001
  366. BNE S1,S5,BFC00444
  367. ADDIU S3,S3,0004
  368. LW A0,0064 (SP)
  369. LW A1,0068 (SP)
  370. BGEZAL R0,BFC0013C
  371. OR A2,S1,R0
  372. @BFC00514: pass control to bootstrap
  373. LW T4,0070 (SP)
  374. LW T6,006C (SP)
  375. LW S0,0018 (SP)
  376. LW S1,001C (SP)
  377. LW S2,0020 (SP)
  378. LW S3,0024 (SP)
  379. LW S4,0028 (SP)
  380. LW S5,002C (SP)
  381. LW S6,0030 (SP)
  382. LW S7,0034 (SP)
  383. LW RA,003C (SP)
  384. OR A0,V0,R0 ;A0 = difference in factors
  385. ADDIU SP,SP,00E0
  386. BGEZAL R0,BFC0056C
  387. XOR A1,T4,T6 ;A1=@SP+70 ^ @SP+6C
  388.  
  389. BFC00550 (A2,A3) = A0 * A1
  390. accepts: A0=value.hi, A1=value.lo, A2=target.hi, A3=target.lo
  391. MULTU A0,A1
  392. MFHI T6
  393. SW T6,0000 (A2)
  394. MFLO T7
  395. SW T7,0000 (A3)
  396. JR RA
  397. NOP
  398.  
  399. BFC0056C pass control to bootstrap
  400. accepts: A0, A1
  401. LUI T3,BFC0
  402. LW T0,07F0 (T3)
  403. LUI T2,FFFF
  404. ANDI A0,A0,FFFF
  405. AND T0,T0,T2
  406. OR A0,A0,T0
  407. ADDIU T3,T3,07C0
  408. @BFC00588
  409. LUI T1,A480
  410. LW T1,0018 (T1)
  411. ANDI T1,T1,0002
  412. BNEL T1,R0,BFC0058C
  413. LUI T1,A480
  414. SW A0,0030 (T3) ;BFC007F0 |= A0
  415. NOP
  416. NOP
  417. NOP
  418. NOP
  419. NOP
  420. @BFC005B4
  421. LUI T1,A480
  422. LW T1,0018 (T1)
  423. ANDI T1,T1,0002
  424. BNEL T1,R0,BFC005B8
  425. LUI T1,A480
  426. LW T0,003C (T3)
  427. ADDIU T1,R0,0020
  428. SW A1,0034 (T3)
  429. OR T0,T0,T1
  430. @BFC005D8
  431. LUI T1,A480
  432. LW T1,0018 (T1)
  433. ANDI T1,T1,0002
  434. BNEL T1,R0,BFC005DC
  435. LUI T1,A480
  436. SW T0,003C (T3) ;BFC007FC |= 0x20
  437. ADDI T1,R0,0010
  438. @BFC005F4 loop while 0x80 not set in BFC007FC
  439. ADDI T1,T1,FFFF
  440. BNEL T1,R0,BFC005F8
  441. ADDI T1,T1,FFFF
  442. LW T0,003C (T3)
  443. ANDI T2,T0,0080
  444. BEQL R0,T2,BFC005F4
  445. ADDI T1,R0,0010
  446. @BFC00610
  447. ADDIU T2,R0,0040
  448. OR T0,T0,T2
  449. LUI T1,A480
  450. LW T1,0018 (T1)
  451. ANDI T1,T1,0002
  452. BNEL T1,R0,BFC0061C
  453. LUI T1,A480
  454. SW T0,003C (T3) ;BFC007FC |= 0x40
  455. LUI T3,A400
  456. ADDIU T3,T3,0000
  457. ADDI T3,T3,0040 ;Jump and execute bootstrap at A4000040
  458. JR T3
  459. NOP
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