Microprocessor

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Engineer:
// Create Date: 20.05.2019 20:50:24
// Module Name: micro_example
// Project Name:
//////////////////////////////////////////////////////////////////////////////////


module micro_example(
    input wire clk, rst,
    input wire PCenable,
    input wire extCtl,
    input wire [3:1] sw,
    output wire[3:0] led,
    output wire[3:0] an,
    output wire[7:0] seg
    );

reg [15:0] monRFData, monInstr, monPC;
wire [3:0] dp_in;
reg [3:0] monRFSrc;

micro my_micro
(
    .clk(clk),
    .reset(rst),
    .PCenable(PCenable),
    .extCtl(extCtl),
    .monRFData(monRFData),
    .monInstr(monInstr),
    .monPC(monPC),
    .monRFSrc(monRFSrc)
);

debounce my_debounce
(
    .clk(clk),
    .reset(rst),
    .sw(sw),
    .db_tick(PCenable),
    .db_level(extCtl)
);

reg [15:0] display;

disp_hex_mux my_disp_hex_mux
(
    .clk(clk),
    .reset(rst),
    .hex3(display[15:12]),
    .hex2(display[11:8]),
    .hex1(display[7:4]),
    .hex0(display[3:0]),
    .dp_in(dp_in),
    .an(an),
    .sseg(seg)
);

always @(posedge clk) begin
    if (sw[0]) begin
        display[15:0] = monInstr[15:0];
    end
    if (sw[1]) begin
        display[15:0] = monPC[15:0];
    end
    if (sw[3]) begin
        display[15:0] = monRFData[15:0];
    end
end

endmodule