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-- Company:
-- Engineer:
--
-- Create Date:    08:29:42 03/21/2019
-- Design Name:
-- Module Name:    Sum - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Sum is
port (
		A, B : in std_logic_vector(3 downto 0); --Entradas 'A & B'
		clock: in STD_LOGIC;
		reset: in STD_LOGIC;
		an: out STD_LOGIC_VECTOR (3 downto 0);
		dec_ddp: out STD_LOGIC_VECTOR (7 downto 0));
end Sum;

architecture Behavioral of Sum is
signal som1 : STD_LOGIC_VECTOR(4 downto 0);
signal d01,d02,d03,d04 : STD_LOGIC_VECTOR (5 downto 0);
begin

s0 : Entity work.somador port map (A => A, B => B, Soma => som1);

--an <= "0111";

s1 : Entity work.dspl_drv port map (clock => clock, reset => reset, d1 => d01, d2 => d02, d3 => d03, d4=> d04, an =>an, dec_ddp => dec_ddp);

d01(0) <= '0';
d02(0) <= '0';
d03(0) <= '0';
d04(0) <= '0';

d01(5) <= '1';
d02(5) <= '1';
d03(5) <= '1';
d04(5) <= '1';

d01(4 downto 1) <= som1;--(4 downto 1);
d02(4 downto 1) <= som1;--(4 downto 1);
d03(4 downto 1) <= som1;--(4 downto 1);
d04(4 downto 1) <= som1;--(4 downto 1);

-- d01 <= '1' & som1 & '0';

end Behavioral;