module program_counter(pc, clk, control, offset);
    input clk;
    input control;
    input [15:0] offset;
    reg extended_offset = 32'b0;
    output reg [31:0] pc = 0;
    always@(posedge clk)
        begin
            extended_offset = $signed(offset);
            case(control)
                0: pc = pc + 4;
                1: pc = pc + (extended_offset*4)+4;
            endcase
        end
endmodule

module data_memory(data_out, mem_write, mem_read, address, data_in);
    output [31:0] data_out;
    input mem_write, mem_read;
    input [31:0] address, data_in;
    reg [255:0] memory [31:0];

    assign data_out = mem_read ? (memory[address]):32'bx;
    always@(mem_write)
        begin
            memory[address] = data_in;
        end
endmodule

module mux_2x1_32b(result,i1,i2,select);
    output reg [31:0] result ;
    input [31:0] i1;
    input [31:0] i2;
    input select ;
    always@(i1, i2, select)
        result = (select)?i1:i2;
endmodule

module instruction_memory(instruction, read_address);
    parameter N = 255;
    output [31:0] instruction;
    input [31:0] read_address;
    reg [31:0] memory [N:0];
    initial
    begin
        $readmemb("instructions.txt", memory);
    end
    assign instruction = memory[read_address];
endmodule

module if_stage(pc, instruction, pcSrc, offset, clk);
    output reg [31:0] pc = 0;
    output [31:0] instruction;

    wire [31:0] _pc;
    input pcSrc, clk;
    input [31:0] offset;

    assign _pc = pc;
    assign instruction = 0;

    always@(posedge clk)
        pc = pcSrc?(pc+(offset*4)):(pc+1);

endmodule

module main;
    reg clk = 1'b0;
    reg pcSrc = 1'b0;
    wire [31:0] pc = 0;
    wire [31:0] instruction = 0;
    reg [31:0] offset = 0;
    if_stage if_stage(pc, instruction, pcSrc, offset, clk);

    initial #300 $finish;
    initial
        begin
            repeat (10)
            #10 clk = ~clk ;
        end

    initial
    begin
        $monitor("Clk:%d, PC:%d, I:%d, PCSrc:%d, Offset:%d", clk, pc, instruction, pcSrc, offset);
    end

endmodule

/*
module main;
    reg clk = 1'b0;
    reg control = 1'b0;
    reg [15:0] offset = 0;
    wire [31:0] pc;

    initial #300 $finish;
    initial
        begin
            repeat (10)
            #10 clk = ~clk ;
        end
    program_counter program(pc, clk, control, offset);
    always@(posedge clk)
        begin
            $display("Clock: %d", clk);
            $display("PC: %d", pc);
            $display("Control: %d", control);
            $display("Offset: %d", offset);
            $display("-------------");
        end
endmodule */