module alu
#(parameter nsumab = 2'b00, nmulab = 2'b01, sumab1 = 2'b10, sumab = 2'b11)

    (input [7:0] a, b,
    input wire clk,
     input [1:0] ctrl,
    output reg [15:0] f);

reg [7:0] c;
always @(posedge clk)
begin
    case (ctrl)
        nsumab:
            begin
                c = a + b;
                f = ~c;
            end
        nmulab:
            begin
                c = a * b;
                f = ~c;
            end
        sumab1:
            begin
                c = a + b;
                f = c + 1'b1;
            end
        sumab:
            begin
                c = ~b;
                f = (a + c) + 1'b1;
            end
        default: f = 0;
    endcase
end
endmodule