`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date:    15:20:57 11/08/2018
// Design Name:
// Module Name:    lcd_driver
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module lcd_driver #(parameter dd = 50000)(input rst, clk, input [15:0] data, input blank,
                        output E, RW, RS, output [7:0] DB);

    wire [1:0] mux_sel, init_sel;

    lcd_controller lcontroller(clk, rst, en,
                             data_sel, DB_sel,
                             init_sel, mux_sel,
                             E, RW, RS);
    clkDiv #(.div(dd)) cdiv(clk, rst, en);
    lcd_dp lcddp(init_sel, mux_sel, data_sel, DB_sel, blank, DB, data);

endmodule