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- module master_slave_D(
- input [0:1] SW,
- output [0:0] LEDR);
- wire Qmaster;
- D_boolean master(~SW[1],SW[0],Qmaster);
- D_boolean slave(SW[1],Qmaster,LEDR[0]);
- endmodule
- module D_boolean(
- input Clk, D,
- output Q);
- wire D_g_1, D_g_2, Qa, Qb;
- assign D_g_1=~(D&Clk);
- assign D_g_2=~(~D&Clk);
- assign Qa=~(D_g_1&Qb);
- assign Qb=~(D_g_2&Qa);
- assign Q=Qa;
- endmodule
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