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Feb 15th, 2019
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  1. panel {
  2. compatible = "ampire,tft-1024600-80-2", "panel-lvds";
  3. pinctrl-names = "default";
  4. pinctrl-0 = <&pinctrl_panel>;
  5. backlight = <&backlight_lvds>;
  6. width-mm = <223>;
  7. height-mm = <125>;
  8. data-mapping = "vesa-24";
  9. enable-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
  10.  
  11. panel-timing {
  12. /* 1024x600 @60Hz */
  13. clock-frequency = <51200000>;
  14. hactive = <1024>;
  15. vactive = <600>;
  16. hsync-len = <16>;
  17. hfront-porch = <64>;
  18. hback-porch = <64>;
  19. vsync-len = <8>;
  20. vfront-porch = <8>;
  21. vback-porch = <8>;
  22. hsync-active = <0>;
  23. vsync-active = <0>;
  24. de-active = <0>;
  25. pixelclk-active = <0>;
  26. assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO>;
  27. };
  28.  
  29. port {
  30. panel_in: endpoint {
  31. remote-endpoint = <&lvds1_out>;
  32. };
  33. };
  34. };
  35.  
  36. clock enable_cnt prepare_cnt rate accuracy phase
  37. ----------------------------------------------------------------------------------------
  38. osc 6 6 24000000 0 0
  39. pll5 0 0 296600000 0 0
  40. pll5_bypass 0 0 296600000 0 0
  41. pll5_video 0 0 296600000 0 0
  42. pll5_post_div 0 0 74150000 0 0
  43. pll5_video_div 0 0 74150000 0 0
  44. ...
  45. pll2 1 1 528000000 0 0
  46. pll2_bypass 1 1 528000000 0 0
  47. pll2_bus 2 2 528000000 0 0
  48. pll2_pfd2_396m 6 6 396000000 0 0
  49. periph2_pre 1 1 396000000 0 0
  50. periph2 1 1 396000000 0 0
  51. mmdc_ch1_axi_podf 1 1 198000000 0 0
  52. mmdc_ch1_axi 1 1 198000000 0 0
  53. ldb_di0_sel 0 0 198000000 0 0
  54. ldb_di0_div_3_5 0 0 56571428 0 0
  55. ldb_di0_podf 0 0 28285714 0 0
  56. ldb_di0 0 0 28285714 0 0
  57. ldb_di1_sel 1 1 198000000 0 0
  58. ldb_di1_div_3_5 1 1 56571428 0 0
  59. ldb_di1_podf 1 1 28285714 0 0
  60. ldb_di1 1 1 28285714 0 0
  61. ipu1_di0_sel 1 1 28285714 0 0
  62. ipu1_di0 1 1 28285714 0 0
  63.  
  64. clock enable_cnt prepare_cnt rate accuracy
  65. ---------------------------------------------------------------------------------
  66. osc 6 6 24000000 0
  67. pll5_bypass_src 1 1 24000000 0
  68. pll5 1 1 716889600 0
  69. pll5_bypass 1 1 716889600 0
  70. pll5_video 1 1 716889600 0
  71. pll5_post_div 1 1 358444800 0
  72. pll5_video_div 1 1 358444800 0
  73. ldb_di1_sel 1 1 358444800 0
  74. ldb_di1_div_7 1 1 51206400 0
  75. ldb_di1_div_sel 1 1 51206400 0
  76. ldb_di1 1 1 51206400 0
  77. ipu1_di1_sel 1 1 51206400 0
  78. ipu1_di1 1 1 51206400 0
  79. ipu1_pclk1_sel 1 1 51206400 0
  80. ipu1_pclk1_div 1 1 51206400 0
  81. ipu1_pclk_1 1 1 51206400 0
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