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  1. `timescale 1ns / 1ps
  2. //////////////////////////////////////////////////////////////////////////////////
  3. // upgineer: Bryan Orabutt
  4. //
  5. // Create Date:    18:07:32 12/31/2014
  6. // Design Name:    Prototype 1
  7. // Module Name:    LED_counter1
  8. // Project Name:   LED Cube Project
  9. // Target Devices: XCSLX9
  10. // Tool versions:  ISE Web Pack 14.7
  11. // Description:    This prototype module uses two counters to continuously blink each LED
  12. //
  13. // Dependupcies:
  14. //
  15. // Revision:
  16. // Revision 0.01 - File Created
  17. // Additional Commupts:
  18. //
  19. //////////////////////////////////////////////////////////////////////////////////
  20. module LED_counter(
  21.     input clk,
  22.     output reg[1:0] level,
  23.     output reg[3:0] column
  24.     );
  25.  
  26. reg [3:0] counter1 = 4'b0000;
  27. reg [1:0] counter2 = 2'b00;
  28. wire c1_max = (counter1 == 4'b1000); //the number of columns in my cube
  29. wire c2_max = (counter2 == 2'b10); //the number of levels in my cube
  30.  
  31. /* Counter to cycle through each column, powering one cloumn with each count
  32. *  and resetting the count when c1_max is a logic high.
  33. */
  34. always @ (posedge clk) begin
  35.         if(c1_max)
  36.                 counter1 <= 4'b0;
  37.         else
  38.                 counter1 <= counter1 + 1;
  39. end
  40.  
  41. /* Counter to cycle through each level, powering the base pin of a single 2N222
  42. *  which causes one level to be connected to GND. Combining this with the column
  43. *  counter means one level + one column is active at a time, meaning one LED is on.
  44. */
  45. always @ (posedge clk) begin
  46.         if(c2_max && c1_max)
  47.                 counter2 <= 2'b00;
  48.         else if(c1_max)
  49.                 counter2 <= counter2 + 1;
  50. end
  51.  
  52. /* Connect the counter values to the output.
  53. */
  54. always @ (posedge clk) begin
  55.                 column <= counter1;
  56.                 level <= counter2;
  57. end
  58.  
  59. endmodule
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