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  1. [ 0.000244] clk_enable_complete: dcxo24M
  2. [ 0.087002] clk_enable_complete: pll-ddr0
  3. [ 0.087300] clk_enable_complete: pll-cpux
  4. [ 0.087328] clk_enable_complete: pll-cpux-div
  5. [ 0.087356] clk_enable_complete: cpux
  6. [ 0.087957] clk_enable_complete: pll-periph0-parent
  7. [ 0.087985] clk_enable_complete: pll-periph0-2x
  8. [ 0.088013] clk_enable_complete: pll-periph0
  9. [ 0.088041] clk_enable_complete: psi-ahb
  10. [ 0.088070] clk_enable_complete: bus-dram
  11. [ 0.089176] clk_enable_complete: bus-mipi-dsi
  12. [ 0.120691] clk_enable_complete: bus-dma
  13. [ 0.120777] clk_enable_complete: mbus
  14. [ 0.120806] clk_enable_complete: mbus-dma
  15. [ 0.191715] clk_enable_complete: apb0
  16. [ 0.221862] clk_enable_complete: bus-de0
  17. [ 0.221922] clk_enable_complete: de0
  18. [ 0.224599] clk_enable_complete: r-apb0
  19. [ 0.224629] clk_enable_complete: r-ppu
  20. [ 0.227026] clk_enable_complete: apb1
  21. [ 0.227055] clk_enable_complete: bus-uart3
  22. [ 1.455793] clk_enable_complete: bus-iommu
  23. [ 1.563322] clk_enable_complete: bus-dpss-top0
  24. [ 1.768760] clk_enable_complete: r-ahb
  25. [ 1.776686] clk_enable_complete: r-ahb-rtc
  26. .....
  27. [ 0.224681] sun20i-ppu 7001000.power-controller: sun20i_ppu_probe: CPU is on
  28. [ 0.224707] sun20i-ppu 7001000.power-controller: sun20i_ppu_probe: VE is on
  29. [ 0.224723] sun20i-ppu 7001000.power-controller: sun20i_ppu_probe: DSP is on
  30. ......
  31. [ 37.206362] [drm:sun4i_crtc_atomic_enable] Enabling the CRTC
  32. [ 37.213255] sun4i-tcon 5461000.lcd-controller: sun4i_tcon_set_status: encoder=DSI-40 enabled
  33. [ 37.222796] regmap_mmio_read: reg=0
  34. [ 37.226704] regmap_mmio_read32le: reg=0
  35. [ 37.231000] regmap_mmio_read32le done
  36. [ 37.235391] regmap_mmio_read: reg=40
  37. [ 37.241080] regmap_mmio_read32le: reg=40
  38. [ 37.245474] regmap_mmio_read32le done
  39. [ 37.249674] clk_prepare: tcon-pixel-clock
  40. [ 37.254230] clk_prepare_complete: tcon-pixel-clock
  41. [ 37.259617] clk_enable: tcon-pixel-clock
  42. [ 37.264016] regmap_mmio_read: reg=44
  43. [ 37.268024] regmap_mmio_read32le: reg=44
  44. [ 37.272419] regmap_mmio_read32le done
  45. [ 37.276530] clk_enable_complete: tcon-pixel-clock
  46. [ 37.282059] sun4i-drm display-engine: [drm:drm_crtc_vblank_on] crtc 0, vblank enabled 0, inmodeset 1
  47. [ 37.292569] [drm:drm_atomic_helper_commit_modeset_enables] enabling [ENCODER:40:DSI-40]
  48. [ 37.301591] [drm:sun6i_dsi_encoder_enable] Enabling DSI output
  49. [ 37.308771] clk_prepare: tcon-top-dsi
  50. [ 37.313394] clk_prepare_complete: tcon-top-dsi
  51. [ 37.318935] clk_enable: tcon-top-dsi
  52. [ 37.322961] clk_enable_complete: tcon-top-dsi
  53. [ 37.328872] clk_prepare: mipi-dsi
  54. [ 37.332611] clk_prepare_complete: mipi-dsi
  55. [ 37.339075] clk_enable: mipi-dsi
  56. [ 37.342721] clk_enable_complete: mipi-dsi
  57. [ 37.348565] clk_set_parent: mipi-dsi pll-periph0
  58. [ 37.354229] clk_set_parent_complete: mipi-dsi pll-periph0
  59. [ 37.360674] clk_set_rate: mipi-dsi 150000000
  60. [ 37.365997] clk_set_rate_complete: mipi-dsi 150000000
  61. [ 37.373108] regmap_mmio_read: reg=54
  62. [ 37.377130] regmap_mmio_read32le: reg=54
  63. [ 37.381528] regmap_mmio_read32le done
  64. [ 37.385956] regmap_mmio_read: reg=54
  65. [ 37.389972] regmap_mmio_read32le: reg=54
  66. [ 37.394368] regmap_mmio_read32le done
  67. [ 37.398846] regmap_mmio_read: reg=5c
  68. [ 37.402859] regmap_mmio_read32le: reg=5c
  69. [ 37.407253] regmap_mmio_read32le done
  70. [ 37.411726] regmap_mmio_read: reg=110
  71. [ 37.415835] regmap_mmio_read32le: reg=110
  72. [ 37.420328] regmap_mmio_read32le done
  73. [ 37.424570] regmap_mmio_read: reg=58
  74. [ 37.428577] regmap_mmio_read32le: reg=58
  75. [ 37.432971] regmap_mmio_read32le done
  76. [ 37.437844] regmap_mmio_read: reg=58
  77. [ 37.441867] regmap_mmio_read32le: reg=58
  78. [ 37.446264] regmap_mmio_read32le done
  79. [ 37.450715] regmap_mmio_read: reg=54
  80. [ 37.454728] regmap_mmio_read32le: reg=54
  81. [ 37.459120] regmap_mmio_read32le done
  82. [ 37.463703] regmap_mmio_read: reg=50
  83. [ 37.467720] regmap_mmio_read32le: reg=50
  84. [ 37.472116] regmap_mmio_read32le done
  85. [ 37.476352] regmap_mmio_read: reg=54
  86. [ 37.480362] regmap_mmio_read32le: reg=54
  87. [ 37.484759] regmap_mmio_read32le done
  88. [ 37.489096] regmap_mmio_read: reg=10
  89. [ 37.493110] regmap_mmio_read32le: reg=10
  90. [ 37.497504] regmap_mmio_read32le done
  91. [ 37.501864] regmap_mmio_read: reg=10
  92. [ 37.505874] regmap_mmio_read32le: reg=10
  93. [ 37.510266] regmap_mmio_read32le done
  94. [ 37.514899] regmap_mmio_read: reg=20
  95. [ 37.518910] regmap_mmio_read32le: reg=20
  96. [ 37.523306] regmap_mmio_read32le done
  97. [ 37.530662] regmap_mmio_read: reg=10
  98. [ 37.534680] regmap_mmio_read32le: reg=10
  99. [ 37.539077] regmap_mmio_read32le done
  100. [ 37.544311] regmap_mmio_read: reg=10
  101. [ 37.548329] regmap_mmio_read32le: reg=10
  102. [ 37.552725] regmap_mmio_read32le done
  103. [ 37.557116] [drm:drm_atomic_helper_commit_planes] drm_atomic_helper_commit_planes: calling atomic_begin
  104. [ 37.567778] [drm:sun4i_crtc_enable_vblank] Enabling VBLANK on crtc 375060e7
  105. [ 37.575590] [drm:sun4i_tcon_enable_vblank] Enabling VBLANK interrupt
  106. [ 37.582716] regmap_mmio_read: reg=4
  107. [ 37.586626] regmap_mmio_read32le: reg=4
  108. [ 37.590924] regmap_mmio_read32le done
  109. [ 37.595046] sun4i-drm display-engine: [drm:drm_vblank_enable] enabling vblank on crtc 0, ret: 0
  110. [ 37.604816] sun4i-drm display-engine: [drm:drm_update_vblank_count] updating vblank count on crtc 0: current=1, diff=0, hw=0 hw_last=0
  111. [ 37.619253] [drm:drm_atomic_helper_commit_planes] drm_atomic_helper_commit_planes: calling atomic_update
  112. [ 37.630035] [drm:sun8i_ui_layer_atomic_update] sun8i_ui_layer_atomic_update
  113. [ 37.638866] [drm:sun8i_ui_layer_atomic_update] sun8i_ui_layer_atomic_update: -> update_coord
  114. [ 37.649212] [drm:sun8i_ui_layer_atomic_update] Updating UI channel 1 overlay 0
  115. [ 37.661890] [drm:sun8i_ui_layer_atomic_update] Layer source offset X: 0 Y: 0
  116. [ 37.671697] [drm:sun8i_ui_layer_atomic_update] Layer source size W: 1200 H: 1920
  117. [ 37.680524] sun8i-mixer 5100000.mixer: 3004 <= 77f04af
  118. [ 37.687354] sun8i-mixer 5100000.mixer: 3088 <= 77f04af
  119. [ 37.698186] [drm:sun8i_ui_layer_atomic_update] HW scaling is not needed
  120. [ 37.711845] sun8i-mixer 5100000.mixer: 40000 <= 0
  121. [ 37.717408] [drm:sun8i_ui_layer_atomic_update] Layer destination coordinates X: 0 Y: 0
  122. [ 37.728120] [drm:sun8i_ui_layer_atomic_update] Layer destination size W: 1200 H: 1920
  123. [ 37.738303] sun8i-mixer 5100000.mixer: 100c <= 0
  124. [ 37.744428] sun8i-mixer 5100000.mixer: 1008 <= 77f04af
  125. [ 37.750214] [drm:sun8i_ui_layer_atomic_update] sun8i_ui_layer_atomic_update: -> update_formats
  126. [ 37.774752] [drm:sun8i_ui_layer_atomic_update] sun8i_ui_layer_atomic_update: -> update_buffer
  127. [ 37.797770] [drm:sun8i_ui_layer_atomic_update] Using GEM @ 0x47100000
  128. [ 37.808574] [drm:sun8i_ui_layer_atomic_update] Layer line width: 4800 bytes
  129. [ 37.817457] sun8i-mixer 5100000.mixer: 300c <= 12c0
  130. [ 37.822954] [drm:sun8i_ui_layer_atomic_update] Setting buffer address to 0x47100000
  131. [ 37.833054] sun8i-mixer 5100000.mixer: 3010 <= 47100000
  132. [ 37.839849] [drm:sun8i_ui_layer_atomic_update] sun8i_ui_layer_atomic_update: -> layer_enable
  133. [ 37.854451] [drm:sun8i_ui_layer_enable] Enabling channel 1 overlay 0
  134. [ 37.862650] sun8i-mixer 5100000.mixer: regmap_update_bits_base: -> map_lock
  135. [ 37.876037] sun8i-mixer 5100000.mixer: regmap_update_bits_base: reg=3000 mask=1 val=1 async=0 force=0
  136. [ 37.887111] sun8i-mixer 5100000.mixer: _regmap_update_bits: calling _regmap_read
  137. [ 37.895416] sun8i-mixer 5100000.mixer: _regmap_read: reg=3000
  138. [ 37.901863] sun8i-mixer 5100000.mixer: _regmap_read: calling reg_read
  139. [ 37.909086] _regmap_bus_reg_read: reg=3000
  140. [ 37.913674] regmap_mmio_read: reg=3000
  141. [ 37.917875] regmap_mmio_read32le: reg=3000
  142. STOPS HERE
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