SHARE
TWEET

Untitled

a guest Apr 21st, 2017 50 Never
Not a member of Pastebin yet? Sign Up, it unlocks many cool features!
  1. ; atmega328p specifics begin (see m238Pdef.inc)
  2. .equ RAMEND, 0x8ff ; highest ram address
  3. .equ SREG, 0x3f   ; cpu status register
  4. .equ SPL, 0x3d    ; stack pointer low byte
  5. .equ SPH, 0x3e    ; stack pointer high byte
  6.  
  7. #define XH r27    ; x pointer reg
  8. #define XL r26
  9. #define YH r29    ; y pointer reg
  10. #define YL r28
  11. #define ZH r31    ; z pointer reg
  12. #define ZL r30
  13.  
  14. ; ***** CPU **************************
  15. ; SREG - Status Register
  16. .equ    SREG_C, 0   ; Carry Flag
  17. .equ    SREG_Z, 1   ; Zero Flag
  18. .equ    SREG_N, 2   ; Negative Flag
  19. .equ    SREG_V, 3   ; Two's Complement Overflow Flag
  20. .equ    SREG_S, 4   ; Sign Bit
  21. .equ    SREG_H, 5   ; Half Carry Flag
  22. .equ    SREG_T, 6   ; Bit Copy Storage
  23. .equ    SREG_I, 7   ; Global Interrupt Enable
  24.  
  25. ;USART register addresses
  26. .equ    UDR0, 0xc6
  27. .equ    UBRR0L, 0xc4
  28. .equ    UBRR0H, 0xc5
  29. .equ    UCSR0C, 0xc2
  30. .equ    UCSR0B, 0xc1
  31. .equ    UCSR0A, 0xc0
  32.  
  33.  
  34. ; ***** USART0 ***********************
  35. ; UDR0 - USART I/O Data Register
  36. .equ    UDR0_0, 0   ; USART I/O Data Register bit 0
  37. .equ    UDR0_1, 1   ; USART I/O Data Register bit 1
  38. .equ    UDR0_2, 2   ; USART I/O Data Register bit 2
  39. .equ    UDR0_3, 3   ; USART I/O Data Register bit 3
  40. .equ    UDR0_4, 4   ; USART I/O Data Register bit 4
  41. .equ    UDR0_5, 5   ; USART I/O Data Register bit 5
  42. .equ    UDR0_6, 6   ; USART I/O Data Register bit 6
  43. .equ    UDR0_7, 7   ; USART I/O Data Register bit 7
  44.  
  45. ; UCSR0A - USART Control and Status Register A
  46. .equ    MPCM0, 0    ; Multi-processor Communication Mode
  47. .equ    U2X0, 1 ; Double the USART transmission speed
  48. .equ    UPE0, 2 ; Parity Error
  49. .equ    DOR0, 3 ; Data overRun
  50. .equ    FE0, 4  ; Framing Error
  51. .equ    UDRE0, 5    ; USART Data Register Empty
  52. .equ    TXC0, 6 ; USART Transmitt Complete
  53. .equ    RXC0, 7 ; USART Receive Complete
  54.  
  55. ; UCSR0B - USART Control and Status Register B
  56. .equ    TXB80, 0    ; Transmit Data Bit 8
  57. .equ    RXB80, 1    ; Receive Data Bit 8
  58. .equ    UCSZ02, 2   ; Character Size
  59. .equ    TXEN0, 3    ; Transmitter Enable
  60. .equ    RXEN0, 4    ; Receiver Enable
  61. .equ    UDRIE0, 5   ; USART Data register Empty Interrupt Enable
  62. .equ    TXCIE0, 6   ; TX Complete Interrupt Enable
  63. .equ    RXCIE0, 7   ; RX Complete Interrupt Enable
  64.  
  65. ; UCSR0C - USART Control and Status Register C
  66. .equ    UCPOL0, 0   ; Clock Polarity
  67. .equ    UCSZ00, 1   ; Character Size
  68. .equ    UCPHA0, UCSZ00  ; For compatibility
  69. .equ    UCSZ01, 2   ; Character Size
  70. .equ    UDORD0, UCSZ01  ; For compatibility
  71. .equ    USBS0, 3    ; Stop Bit Select
  72. .equ    UPM00, 4    ; Parity Mode Bit 0
  73. .equ    UPM01, 5    ; Parity Mode Bit 1
  74. .equ    UMSEL00, 6  ; USART Mode Select
  75. .equ    UMSEL0, UMSEL00 ; For compatibility
  76. .equ    UMSEL01, 7  ; USART Mode Select
  77. .equ    UMSEL1, UMSEL01 ; For compatibility
  78.  
  79. ; UBRR0H - USART Baud Rate Register High Byte
  80. .equ    UBRR8, 0    ; USART Baud Rate Register bit 8
  81. .equ    UBRR9, 1    ; USART Baud Rate Register bit 9
  82. .equ    UBRR10, 2   ; USART Baud Rate Register bit 10
  83. .equ    UBRR11, 3   ; USART Baud Rate Register bit 11
  84.  
  85. ; UBRR0L - USART Baud Rate Register Low Byte
  86. .equ    _UBRR0, 0   ; USART Baud Rate Register bit 0
  87. .equ    _UBRR1, 1   ; USART Baud Rate Register bit 1
  88. .equ    UBRR2, 2    ; USART Baud Rate Register bit 2
  89. .equ    UBRR3, 3    ; USART Baud Rate Register bit 3
  90. .equ    UBRR4, 4    ; USART Baud Rate Register bit 4
  91. .equ    UBRR5, 5    ; USART Baud Rate Register bit 5
  92. .equ    UBRR6, 6    ; USART Baud Rate Register bit 6
  93. .equ    UBRR7, 7    ; USART Baud Rate Register bit 7
  94.  
  95. ; atmega328p specifics end
  96. .org 0
  97.    rjmp main
  98.  
  99.  main:
  100.     ; reset system status
  101.     ldi r16,0
  102.     out SREG,r16
  103.  
  104.     ; init stack pointer
  105.     ldi r16,lo8(RAMEND)
  106.     out SPL,r16
  107.     ldi r16,hi8(RAMEND)
  108.     out SPH,r16
  109.  
  110.     rcall init_uart
  111.     rjmp mainloop
  112.  
  113. init_uart:
  114.   ; set baud rate 1 Mbps
  115.   ldi r16, 1<<U2X0
  116.   sts UCSR0A, r16
  117.   ldi r16, 0
  118.   sts UBRR0H, r16
  119.   ldi r16, 1
  120.   sts UBRR0L, r16
  121.  
  122.   ; enable receive and transmit, without interrupts
  123.   ldi r16, (1<<RXEN0)|(1<<TXEN0)
  124.   sts UCSR0B,r16
  125.  
  126.   ; frame format: 8 data bits, 1 stop bit, no parity.
  127.   ldi r16, (1<<UCSZ01)|(1<<UCSZ00)
  128.   sts UCSR0C,r16
  129.  
  130.   ret
  131.  
  132. ; sends one byte over the serial line.
  133. ; data must reside in r17.
  134. send_byte:
  135.   ; wait for UDR to become empty
  136.   lds r16, UCSR0A
  137.   sbrs r16, UDRE0
  138.   rjmp send_byte
  139.  
  140.   ; write data to transmit register
  141.   sts UDR0, R17
  142.  
  143.   ret
  144.  
  145. ; 3M cycle delay (~ 0.19s)
  146. wait:
  147.   ldi r21,0x10
  148.   ldi r22,0x00
  149.   ldi r23,0x00
  150.  
  151. _wait_loop:
  152.   dec r23
  153.   brne _wait_loop
  154.   dec r22
  155.   brne _wait_loop
  156.   dec r21
  157.   brne _wait_loop
  158.  
  159.   ret
  160.  
  161. mainloop:
  162.   ldi r17, 'H'
  163.   call send_byte
  164.   ldi r17, 'e'
  165.   call send_byte
  166.   ldi r17, 'l'
  167.   call send_byte
  168.   ldi r17, 'l'
  169.   call send_byte
  170.   ldi r17, 'o'
  171.   call send_byte
  172.   ldi r17, '!'
  173.   call send_byte
  174.  
  175.   call wait
  176.  
  177.   rjmp mainloop
RAW Paste Data
Top